Inventor
CARNEY CHRISTOPHER M
US5 patents
Patents
5 patentsUS7480886B2Jan 20, 2009
VLSI timing optimization with interleaved buffer insertion and wire sizing stages
IBM11 citations77
US7469399B2Dec 23, 2008
Semi-flattened pin optimization process for hierarchical physical designs
IBM3 citations59
US7882472B2Feb 1, 2011
Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process
IBM4 citations55
US7809874B2Oct 5, 2010
Method for resource sharing in a multiple pipeline environment
IBM0 citations40
US7752585B2Jul 6, 2010
Method, apparatus, and computer program product for stale NDR detection
IBM0 citations35