Inventor
SHARANGPANI HARSHVARDHAN P
US11 patents
Patents
11 patentsUS5860017AJan 12, 1999
Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
INTEL CORP182 citations98
US5699537ADec 16, 1997
Processor microarchitecture for efficient dynamic scheduling and execution of chains of dependent instructions
INTEL CORP242 citations97
US6553488B2Apr 22, 2003
Method and apparatus for branch prediction using first and second level branch prediction tables
INTEL CORP53 citations96
US6065115AMay 16, 2000
Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
INTEL CORP78 citations96
US5978737ANov 2, 1999
Method and apparatus for hazard detection and distraction avoidance for a vehicle
INTEL CORP63 citations96
US5522051AMay 28, 1996
Method and apparatus for stack manipulation in a pipelined processor
INTEL CORP68 citations95
US5367650ANov 22, 1994
Method and apparauts for parallel exchange operation in a pipelined processor
INTEL CORP73 citations94
US5832260ANov 3, 1998
Processor microarchitecture for efficient processing of instructions in a program including a conditional program flow control instruction
INTEL CORP44 citations92
US5559977ASep 24, 1996
Method and apparatus for executing floating point (FP) instruction pairs in a pipelined processor by stalling the following FP instructions in an execution stage
INTEL CORP51 citations90
US5590359ADec 31, 1996
Method and apparatus for generating a status word in a pipelined processor
INTEL CORP16 citations73
US6401195B1Jun 4, 2002
Method and apparatus for replacing data in an operand latch of a pipeline stage in a processor during a stall
INTEL CORP12 citations71