Inventor

DYBSETTER GERALD L

US56 patents

⚠️ This page may combine multiple inventors who share the name “DYBSETTER GERALD L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DYBSETTER GERALD L

FINISAR CORP

Configurable two-wire interface module

Volatile memory persistence during warm reboot in an optical transceiver

Inter-transceiver module communication for optimization of link between transceivers

Microcode-driven self-calibration of optical transceivers to environmental conditions

Analog to digital signal conditioning in optoelectronic transceivers

Module command interface for an optical transceiver

Interface architecture for facilitating communication regardless of protocol

Transceiver based loop back initiation

Multi-transceiver module control with single microcontroller

Early self-validation of persistent memory during boot in an optical transceiver

Microcode-driven calculation of temperature-dependent operational parameters in an optical transmitter/receiver

Protocol specific transceiver firmware

Transceiver with persistent logging mechanism

Microcode driven adjustment of analog-to-digital converter

Encrypted microcode update of an optical transceiver

Two-wire interface having dynamically adjustable data fields depending on operation code

Access key enabled update of an optical transceiver

Transaction for transceiver firmware download

Configurable optical transceiver feature specific cost transaction

Off-module optical transceiver firmware paging

Microcode configurable frequency clock

Host printed circuit board with multiple optical transceivers

Multiple bus interface control using a single controller

Optical transceiver with custom logging mechanism

Adjustable boot speed in an optical transceiver

Watch-dog instruction embedded in microcode

Calibration of digital diagnostics information in an optical transceiver prior to reporting to host

Configurable input/output terminals

Microcode-driven programmable receive power levels in an optical transceiver

Two-wire interface having embedded per frame reliability information

Integrated post-amplifier, laser driver, and controller

Self-testing optical transceiver controller using internalized loopbacks

Background consistency checking in an optical transceiver

Single operation per-bit memory access

Transient transceiver clock configuration

Use of a third state applied to a digital input terminal of a circuit to initiate non-standard operational modes of the circuit

DYBSETTER GERALD L

Two-wire interface in which a master component monitors the data line during the preamble generation phase for synchronization with one or more slave components

Self-testing optical transceiver

Use of a first two-wire interface communication to support the construction of a second two-wire interface communication

Early self-validation of persistent memory during boot in an optical transceiver

Byte-configurable memory in an optical transceiver

Microcode configurable frequency clock

Multi-level memory access in an optical transceiver

EKKIZOGLOY LUKE M

Inter-transceiver module communication for firmware upgrade

Inter-transceiver module communication for optimization of link between transceivers

Optical transceiver with vendor authentication

Inter-transceiver module communication for firmware upgrade

Filtering digital diagnostics information in an optical transceiver prior to reporting to host

HAHIN JAYNE C

Configuration of optical transceivers to perform custom features

EKKISOGLOY LUKE M

Optical transceiver with off-transceiver logging mechanism