Inventor
TATE NAOTO
US18 patents
⚠️ This page may combine multiple inventors who share the name “TATE NAOTO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SHINETSU HANDOTAI KK
11 patentsUS6372609B1Apr 16, 2002
Method of Fabricating SOI wafer by hydrogen ION delamination method and SOI wafer fabricated by the method
SHINETSU HANDOTAI KK512 citations99
US6596610B1Jul 22, 2003
Method for reclaiming delaminated wafer and reclaimed delaminated wafer
SHINETSU HANDOTAI KK108 citations97
US5749974AMay 12, 1998
Method of chemical vapor deposition and reactor therefor
SHINETSU HANDOTAI KK101 citations97
US6284629B1Sep 4, 2001
Method of fabricating an SOI wafer and SOI wafer fabricated by the method
SHINETSU HANDOTAI KK78 citations96
US6846718B1Jan 25, 2005
Method for producing SOI wafer and SOI wafer
SHINETSU HANDOTAI KK42 citations92
US6720640B2Apr 13, 2004
Method for reclaiming delaminated wafer and reclaimed delaminated wafer
SHINETSU HANDOTAI KK25 citations92
US5938840AAug 17, 1999
Method for vapor phase growth
SHINETSU HANDOTAI KK17 citations92
US5755878AMay 26, 1998
Method for vapor phase growth
SHINETSU HANDOTAI KK30 citations92
US6897124B2May 24, 2005
Method of manufacturing a bonded wafers using a Bernoulli chuck
SHINETSU HANDOTAI KK5 citations63
US5718762AFeb 17, 1998
Method for vapor-phase growth
SHINETSU HANDOTAI KK5 citations62
US6048793AApr 11, 2000
Method and apparatus for thin film growth
SHINETSU HANDOTAI KK1 citations51
SEH AMERICA INC
3 patentsUS6022793AFeb 8, 2000
Silicon and oxygen ion co-implantation for metallic gettering in epitaxial wafers
SEH AMERICA INC84 citations95
US6569749B1May 27, 2003
Silicon and oxygen ion co-implanation for metallic gettering in epitaxial wafers
SEH AMERICA INC12 citations73
US5764353AJun 9, 1998
Back side damage monitoring system
SEH AMERICA INC16 citations70
SOITEC SILICON ON INSULATOR
2 patentsUS7288418B2Oct 30, 2007
Process for treating substrates for the microelectronics industry, and substrates obtained by this process
SOITEC SILICON ON INSULATOR20 citations91
US7029993B1Apr 18, 2006
Method for treating substrates for microelectronics and substrates obtained according to said method
SOITEC SILICON ON INSULATOR31 citations91