Inventor
MARCELLA JAMES ANTHONY
US21 patents
⚠️ This page may combine multiple inventors who share the name “MARCELLA JAMES ANTHONY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS6557069B1Apr 29, 2003
Processor-memory bus architecture for supporting multiple processors
IBM169 citations99
US6526469B1Feb 25, 2003
Bus architecture employing varying width uni-directional command bus
IBM198 citations99
US6513091B1Jan 28, 2003
Data routing using status-response signals
IBM167 citations98
US6247100B1Jun 12, 2001
Method and system for transmitting address commands in a multiprocessor system
IBM120 citations98
US6895482B1May 17, 2005
Reordering and flushing commands in a computer memory subsystem
IBM79 citations97
US7254663B2Aug 7, 2007
Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes
IBM46 citations96
US6760856B1Jul 6, 2004
Programmable compensated delay for DDR SDRAM interface using programmable delay loop for reference calibration
IBM70 citations96
US6940760B2Sep 6, 2005
Data strobe gating for source synchronous communications interface
IBM58 citations95
US6671211B2Dec 30, 2003
Data strobe gating for source synchronous communications interface
IBM20 citations92
US6628662B1Sep 30, 2003
Method and system for multilevel arbitration in a non-blocking crossbar switch
IBM52 citations92
US6505306B1Jan 7, 2003
Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initialization
IBM31 citations92
US7873773B2Jan 18, 2011
Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes
IBM7 citations84
US7234017B2Jun 19, 2007
Computer system architecture for a processor connected to a high speed bus transceiver
IBM14 citations81
US7526692B2Apr 28, 2009
Diagnostic interface architecture for memory device
IBM6 citations73
US6188627B1Feb 13, 2001
Method and system for improving DRAM subsystem performance using burst refresh control
IBM11 citations73
US7802158B2Sep 21, 2010
Diagnostic interface architecture for memory device
IBM3 citations62
US6963516B2Nov 8, 2005
Dynamic optimization of latency and bandwidth on DRAM interfaces
IBM6 citations62
US6185646B1Feb 6, 2001
Method and apparatus for transferring data on a synchronous multi-drop
IBM2 citations62
US6523080B1Feb 18, 2003
Shared bus non-sequential data ordering method and apparatus
IBM2 citations61
US5748919AMay 5, 1998
Shared bus non-sequential data ordering method and apparatus
IBM1 citations51