Inventor

PUGH DANIEL J

US13 patents

⚠️ This page may combine multiple inventors who share the name “PUGH DANIEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TABULA INC

6 patents

US7372297B1May 13, 2008

Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources

TABULA INC59 citations97

US7971172B1Jun 28, 2011

IC that efficiently replicates a function to save logic and routing resources

TABULA INC22 citations92

US7587697B1Sep 8, 2009

System and method of mapping memory blocks in a configurable integrated circuit

TABULA INC33 citations92

US7930666B1Apr 19, 2011

System and method of providing a memory hierarchy

TABULA INC11 citations84

US7818361B1Oct 19, 2010

Method and apparatus for performing two's complement multiplication

TABULA INC8 citations83

US7765249B1Jul 27, 2010

Use of hybrid interconnect/logic circuits for multiplication

TABULA INC6 citations63

INTEL CORP

3 patents

US6834291B1Dec 21, 2004

Gold code generator design

INTEL CORP15 citations90

US6904105B1Jun 7, 2005

Method and implemention of a traceback-free parallel viterbi decoder

INTEL CORP4 citations62

US7080107B2Jul 18, 2006

Gold code generator design

INTEL CORP2 citations60

LEOPARD LOGIC INC

1 patent

US6801052B2Oct 5, 2004

Field programmable gate array core cell with efficient logic packing

LEOPARD LOGIC INC14 citations81

PUGH DANIEL J

1 patent

US8463836B1Jun 11, 2013

Performing mathematical and logical operations in multiple sub-cycles

PUGH DANIEL J13 citations80

SCHMIT HERMAN

1 patent

US8434045B1Apr 30, 2013

System and method of providing a memory hierarchy

SCHMIT HERMAN2 citations62

AGATE LOGIC INC

1 patent

US7009421B2Mar 7, 2006

Field programmable gate array core cell with efficient logic packing

AGATE LOGIC INC4 citations60