Inventor
CHIRANIA MANOJ
US18 patents
Patents
18 patentsUS6998872B1Feb 14, 2006
Lookup table circuit optionally configurable as two or more smaller lookup tables with independent inputs
XILINX INC252 citations99
US7804719B1Sep 28, 2010
Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode
XILINX INC80 citations98
US7116131B1Oct 3, 2006
High performance programmable logic devices utilizing dynamic circuitry
XILINX INC107 citations98
US7653891B1Jan 26, 2010
Method of reducing power of a circuit
XILINX INC58 citations97
US7375552B1May 20, 2008
Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure
XILINX INC26 citations92
US7265576B1Sep 4, 2007
Programmable lookup table with dual input and output terminals in RAM mode
XILINX INC19 citations92
US7215138B1May 8, 2007
Programmable lookup table with dual input and output terminals in shift register mode
XILINX INC25 citations92
US7268587B1Sep 11, 2007
Programmable logic block with carry chains providing lookahead functions of different lengths
XILINX INC25 citations91
US7518394B1Apr 14, 2009
Process monitor vehicle
XILINX INC8 citations84
US7471104B1Dec 30, 2008
Lookup table with relatively balanced delays
XILINX INC12 citations84
US7385416B1Jun 10, 2008
Circuits and methods of implementing flip-flops in dual-output lookup tables
XILINX INC15 citations84
US7202697B1Apr 10, 2007
Programmable logic block having improved performance when functioning in shift register mode
XILINX INC17 citations84
US7119570B1Oct 10, 2006
Method of measuring performance of a semiconductor device and circuit for the same
XILINX INC14 citations83
US7382157B1Jun 3, 2008
Interconnect driver circuits for dynamic logic
XILINX INC2 citations63
US7378869B1May 27, 2008
Lookup table circuits programmable to implement flip-flops
XILINX INC3 citations63
US7552410B1Jun 23, 2009
Estimating LUT power usage
XILINX INC3 citations62
US7423452B1Sep 9, 2008
Integrated circuit including a multiplexer circuit
XILINX INC2 citations62
US7600204B1Oct 6, 2009
Method for simulation of negative bias and temperature instability
XILINX INC3 citations58