Inventor
LIN LI-TE S
TW21 patents
⚠️ This page may combine multiple inventors who share the name “LIN LI-TE S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
17 patentsUS6720256B1Apr 13, 2004
Method of dual damascene patterning
TAIWAN SEMICONDUCTOR MFG78 citations98
US7494884B2Feb 24, 2009
SiGe selective growth without a hard mask
TAIWAN SEMICONDUCTOR MFG36 citations92
US6797630B1Sep 28, 2004
Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approach
TAIWAN SEMICONDUCTOR MFG20 citations92
US6495469B1Dec 17, 2002
High selectivity, low etch depth micro-loading process for non stop layer damascene etch
TAIWAN SEMICONDUCTOR MFG20 citations92
US6376366B1Apr 23, 2002
Partial hard mask open process for hard mask dual damascene etch
TAIWAN SEMICONDUCTOR MFG49 citations92
US7838887B2Nov 23, 2010
Source/drain carbon implant and RTA anneal, pre-SiGe deposition
TAIWAN SEMICONDUCTOR MFG26 citations91
US6794302B1Sep 21, 2004
Dynamic feed forward temperature control to achieve CD etching uniformity
TAIWAN SEMICONDUCTOR MFG21 citations90
US6797627B1Sep 28, 2004
Dry-wet-dry solvent-free process after stop layer etch in dual damascene process
TAIWAN SEMICONDUCTOR MFG35 citations88
US7816217B2Oct 19, 2010
Multi-step epitaxial process for depositing Si/SiGe
TAIWAN SEMICONDUCTOR MFG17 citations84
US7612389B2Nov 3, 2009
Embedded SiGe stressor with tensile strain for NMOS current enhancement
TAIWAN SEMICONDUCTOR MFG9 citations84
US6849531B1Feb 1, 2005
Phosphoric acid free process for polysilicon gate definition
TAIWAN SEMICONDUCTOR MFG15 citations82
US8039375B2Oct 18, 2011
Shallow junction formation and high dopant activation rate of MOS devices
TAIWAN SEMICONDUCTOR MFG2 citations63
US6864174B2Mar 8, 2005
Iteratively selective gas flow control and dynamic database to achieve CD uniformity
TAIWAN SEMICONDUCTOR MFG7 citations63
US6835578B1Dec 28, 2004
Test structure for differentiating the line and via contribution in stress migration
TAIWAN SEMICONDUCTOR MFG4 citations62
US7179715B2Feb 20, 2007
Method for controlling spacer oxide loss
TAIWAN SEMICONDUCTOR MFG5 citations53
US9196491B2Nov 24, 2015
End-cut first approach for critical dimension control
TAIWAN SEMICONDUCTOR MFG0 citations51
US7307009B2Dec 11, 2007
Phosphoric acid free process for polysilicon gate definition
TAIWAN SEMICONDUCTOR MFG0 citations50