Inventor

CHEN HUAJIE

US62 patents

⚠️ This page may combine multiple inventors who share the name “CHEN HUAJIE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN HUAJIE

IBM

High performance CMOS device structure with mid-gap metal gate

Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Metal oxide field effect transistor with a sharp halo

Chemical treatment to retard diffusion in a semiconductor overlayer

Method of preventing surface roughening during hydrogen prebake of SiGe substrates

High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

Structure and method for making strained channel field effect transistor using sacrificial spacer

Method of Forming strained SI/SIGE on insulator with silicon germanium buffer

High performance CMOS device structure with mid-gap metal gate

Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions

Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer

Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance

Thin channel FET with recessed source/drains and extensions

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels

In situ doped embedded sige extension and source/drain for enhanced PFET performance

BiCMOS integration scheme with raised extrinsic base

Nitride pedestal for raised extrinsic base HBT process

Method of forming thin SGOI wafers with high relaxation and low stacking fault defect density

Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering

Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:C

Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

High-quality SGOI by annealing near the alloy melting point

Buffer layer for selective SiGe growth for uniform nucleation

Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels

SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowth

Use of thin SOI to inhibit relaxation of SiGe layers

Method of fabricating strained Si SOI wafers

Method of making strained channel CMOS transistors having lattice-mismatched epitaxial

Hybrid SOI/bulk semiconductor transistors

Hybrid SOI/bulk semiconductor transistors

Structure and method for making strained channel field effect transistor using sacrificial spacer

Hybrid SOI-bulk semiconductor transistors

Ultra shallow junction formation by epitaxial interface limited diffusion

Defect reduction by oxidation of silicon

Self-aligned mask formed utilizing differential oxidation rates of materials

Method of forming strained silicon materials with improved thermal conductivity

Method for improving CVD film quality utilizing polysilicon getterer

Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification

Defect reduction by oxidation of silicon

Structure and method for reducing threshold voltage variation

Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels

Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI MOS devices by gate stress engineering with SiGe and/or Si:C

Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance

High-quality SGOI by annealing near the alloy melting point

Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer

HUANG HUI

Motor and rotor thereof

Motor rotor and motor having same

Motor rotor and motor having same