Inventor

JENG SHIN-PUU

TW728 patents

⚠️ This page may combine multiple inventors who share the name “JENG SHIN-PUU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JENG SHIN-PUU

APPLIED MATERIALS INC

Method of decreasing the K value in SiOC layer deposited by chemical vapor deposition

Plasma processes for depositing low dielectric constant films

Plasma processes for depositing low dielectric constant films

Plasma processes for depositing low dielectric constant films

Method of depositing a low K dielectric with organo silane

Method of depositing a low k dielectric with organo silane

Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound

Plasma processes for depositing low dielectric constant films

Plasma processes for depositing low dielectric constant films

Low power method of depositing a low k dielectric with organo silane

Method of depositing a low k dielectric with organo silane

Plasma processes for depositing low dielectric constant films

Plasma processes for depositing low dielectric constant films

Plasma enhanced chemical vapor deposition of copolymer of parylene N and comonomers with various double bonds

Chemical vapor deposition of a copolymer of p-xylylene and a multivinyl silicon/oxygen comonomer

Low dielectric constant film produced from silicon compounds comprising silicon-carbon bonds

Plasma processes for depositing low dielectric constant films

Method of depositing a low dielectric with organo silane

Method of depositing a low K dielectric with organo silane

TEXAS INSTRUMENTS INC

Multilevel interconnect structure with air gaps formed between metal leads

Method of making an interconnect structure with an integrated low density dielectric

Multilevel interconnect structure with air gaps formed between metal leads

Low capacitance interconnect structure for integrated circuits

Semiconductor device having damascene interconnects

Porous insulator for line-to-line capacitance reduction

Low volatility solvent-based method for forming thin film nanoporous aerogels on semiconductor substrates

Low volatility solvent-based method for forming thin film nanoporous aerogels on semiconductor substrates

Nanoporous dielectric thin film formation using a post-deposition catalyst

Nanoporous dielectric thin film surface modification

Method of forming diffusion barriers encapsulating copper

Multilevel interconnect structure with air gaps formed between metal leads

Barrier-less plug structure

Porous insulator for line-to-line capacitance reduction

Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials

TAIWAN SEMICONDUCTOR MFG

Testing of semiconductor chips with microbumps

3D packages and methods for forming the same

Structure and method for 3D IC package

3D packages and methods for forming the same

Multi-die stacking using bumps with different sizes

Method and apparatus for enhanced CMP planarization using surrounded dummy design

TAIWAN SEMICONDUCTOR MFG CO LTD

Electric magnetic shielding structure in packages

Semiconductor structure and manufacturing method thereof

YU CHEN-HUA

Interconnect structure for wafer level package

HUNG JUI-PIN

Packaging methods and structures using a die attach film

WU WEI-CHENG

Package systems having interposers

LIN JING-CHENG

Packages including active dies and dummy dies and methods for forming the same

JENG SHIN-PUU

3D semiconductor package interposer with die cavity

SHIH YING-CHING

Embedded 3D interposer structure

HU HSIEN-PIN

Approach for bonding dies onto interposers

LIU TZUAN-HORNG

Interposer test structures and methods