Inventor
SOLOMON PAUL MICHAEL
US23 patents
⚠️ This page may combine multiple inventors who share the name “SOLOMON PAUL MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
22 patentsUS5773331AJun 30, 1998
Method for making single and double gate field effect transistors with sidewall source-drain contacts
IBM192 citations99
US9852790B1Dec 26, 2017
Circuit methodology for highly linear and symmetric resistive processing unit
IBM59 citations98
US6057212AMay 2, 2000
Method for making bonded metal back-plane substrates
IBM388 citations98
US5960265ASep 28, 1999
Method of making EEPROM having coplanar on-insulator FET and control gate
IBM163 citations98
US5886376AMar 23, 1999
EEPROM having coplanar on-insulator FET and control gate
IBM251 citations98
US6645861B2Nov 11, 2003
Self-aligned silicide process for silicon sidewall source and drain contacts
IBM71 citations96
US6555880B2Apr 29, 2003
Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
IBM54 citations96
US10269425B2Apr 23, 2019
Circuit methodology for highly linear and symmetric resistive processing unit
IBM13 citations92
US6987050B2Jan 17, 2006
Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow junctions
IBM21 citations92
US6716708B2Apr 6, 2004
Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
IBM20 citations92
US6005415ADec 21, 1999
Switching circuit for large voltages
IBM20 citations92
US7498640B2Mar 3, 2009
Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby
IBM5 citations74
US10950304B2Mar 16, 2021
Circuit methodology for highly linear and symmetric resistive processing unit
IBM2 citations73
US6281551B1Aug 28, 2001
Back-plane for semiconductor device
IBM6 citations72
US12568776B2Mar 3, 2026
Multifilament resistive memory with insulation layers
IBM0 citations62
US11842770B2Dec 12, 2023
Circuit methodology for highly linear and symmetric resistive processing unit
IBM0 citations62
US11823740B2Nov 21, 2023
Selective application of multiple pulse durations to crossbar arrays
IBM0 citations62
US11568927B2Jan 31, 2023
Two-terminal non-volatile memory cell for decoupled read and write operations
IBM0 citations62
US10896979B2Jan 19, 2021
Compact vertical injection punch through floating gate analog memory and a manufacture thereof
IBM0 citations62
US12475961B2Nov 18, 2025
Fractal analog random access memory
IBM0 citations56
US12550632B2Feb 10, 2026
Resistive memory with resistance spreading layer
IBM0 citations52
US11250316B2Feb 15, 2022
Aggregate adjustments in a cross bar neural network
IBM0 citations52