Inventor
JHA ASHISH KUMAR
IN12 patents
⚠️ This page may combine multiple inventors who share the name “JHA ASHISH KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
7 patentsUS9443771B1Sep 13, 2016
Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology
GLOBALFOUNDRIES INC10 citations84
US10396206B2Aug 27, 2019
Gate cut method
GLOBALFOUNDRIES INC7 citations83
US9331159B1May 3, 2016
Fabricating transistor(s) with raised active regions having angled upper surfaces
GLOBALFOUNDRIES INC10 citations82
US10192746B1Jan 29, 2019
STI inner spacer to mitigate SDB loading
GLOBALFOUNDRIES INC12 citations80
US10522679B2Dec 31, 2019
Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures
GLOBALFOUNDRIES INC6 citations69
US10008385B1Jun 26, 2018
Enlarged sacrificial gate caps for forming self-aligned contacts
GLOBALFOUNDRIES INC1 citations51
US9147572B2Sep 29, 2015
Using sacrificial oxide layer for gate length tuning and resulting device
GLOBALFOUNDRIES INC0 citations51