Inventor

WU XIAOJU

US47 patents

⚠️ This page may combine multiple inventors who share the name “WU XIAOJU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WU XIAOJU

TEXAS INSTRUMENTS INC

Method of manufacturing and structure of semiconductor device with field oxide structure

Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to build this device

Method for manufacturing a MOS transistor having reduced 1/f noise

Drain centered LDMOS transistor with integrated dummy patterns

ESD protection circuit with isolated SCR for negative voltage operation

Deep buried channel junction field effect transistor (DBCJFET)

Area-efficient electrically erasable programmable memory cell

Automatic gain control

One time programmable EPROM fabrication in STI CMOS technology

Method for manufacturing and structure of semiconductor device with polysilicon definition structure

Drain extended NMOS transistor

Drain extended NMOS transistor

Drain extended transistor

Integrated circuit device with a vertical JFET

Method for manufacturing and structure of semiconductor device with polysilicon definition structure

ESD protection circuit with isolated SCR for negative voltage operation

ESD protection circuit with isolated SCR for negative voltage operation

ESD protection circuit with isolated SCR for negative voltage operation

Method to detect poly residues in LOCOS process

EEPROM with etched tunneling window

Fabrication of an OTP-EPROM having reduced leakage current

High reliability polysilicon components

High reliability polysilicon components

Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same

Gate self aligned low noise JFET

Protection of drain extended transistor field oxide

P-channel DEMOS device

Semiconductor device with extended electrically-safe operating area

Semiconductor device with extended electrically-safe operating area

ESD protection circuit with isolated SCR for negative voltage operation

Semiconductor device with extended electrically-safe operating area

P-channel DEMOS device

Area efficient differential EEPROM cell with improved data retention and read/write endurance

Method of manufacturing and structure of semiconductor device (DEMOS) with field oxide structure

Drain centered LDMOS transistor with integrated dummy patterns

MOSFET transistors with robust subthreshold operations

MOSFET transistors with robust subthreshold operations

Method for detecting epitaxial (EPI) induced buried layer shifts in semiconductor devices

Shallow trench isolation processing with local oxidation of silicon

Body bias to facilitate transistor matching

Output driver with power down protection

WU XIAOJU

Area-efficient electrically erasable programmable memory cell

Area-efficient electrically erasable programmable memory cell

CHATTERJEE AMITAVA

Methods for reducing gate dielectric thinning on trench isolation edges and integrated circuits therefrom

MITROS JOZEF CZESLAW

Single poly EEPROM without separate control gate nor erase regions

LIN MIN

Catalyst and the preparation process thereof and a process for epoxidising olefin

LI HUA

Process for producing an alkylene oxide by olefin epoxidation