Inventor

HAO PINGHAI

US47 patents

⚠️ This page may combine multiple inventors who share the name “HAO PINGHAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAO PINGHAI

TEXAS INSTRUMENTS INC

Quasi-vertical gated NPN-PNP ESD protection device

Symmetrical bi-directional semiconductor ESD protection device

Drain extended MOS devices with self-aligned floating region and fabrication methods therefor

JFET structure for integrated circuit and fabrication method

Low noise vertical variable gate control voltage JFET device in a BiCMOS process and methods to build this device

Method for manufacturing a MOS transistor having reduced 1/f noise

Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process

Depletion drain-extended MOS transistors and methods for making the same

Recessed solid state apparatuses

Methods of fabricating high voltage devices

High voltage CMOS with triple gate oxide

High voltage CMOS with triple gate oxide

Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure

High voltage transistor using diluted drain

Integration of high voltage JFET in linear bipolar CMOS process

Integrated circuit device with a vertical JFET

Gallium nitride transistor with a doped region

Gallium nitride transistor with a doped region

HEMT wafer probe current collapse screening

Gallium nitride transistor with a doped region

EEPROM with etched tunneling window

Fabrication of an OTP-EPROM having reduced leakage current

Low noise JFET

JFET structure for integrated circuit and fabrication method

Threshold voltage stabilizer, method of manufacturing and integrated circuit employing the same

Capacitor having a dielectric layer including a group 17 element

Semiconductor device including a dielectric layer having a gettering material located therein and a method of manufacture therefor

Gate self aligned low noise JFET

Transistor with multiple GaN-based alloy layers

Recessed solid state apparatuses

Single photomask high precision thin film resistor

Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure

Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure

Single photomask high precision thin film resistor

Low cost transistors

Low cost transistors

Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure

Reduction of channel hot carrier effects in transistor devices

Reduction of channel hot carrier effects in transistor devices

High voltage CMOS with triple gate oxide

DEMOS formed with a through gate implant

HAO PINGHAI

High voltage transistor using diluted drain

Implanted well breakdown in high voltage devices

Low noise JFET

HU BINGHUA

JFET having width defined by trench isolation

DENISON MARIE

Quasi-vertical gated NPN-PNP ESD protection device

MITROS JOZEF C

Reduced area single poly EEPROM