Inventor

MEADE ROY EDWARD

US45 patents

Patents

45 patents

US10330875B2Jun 25, 2019

MEADE ROY EDWARD

Patents

Optical module and associated methods

Pooled DRAM system enabled by monolithic in-package optical I/O

Multi-chip packaging of silicon photonics

Fiber attach enabled wafer level fanout

Optical module and associated methods

Vertical integrated photonics chiplet for in-package optical interconnect

Wafer-level etching methods for planar photonics circuits and devices

Optical multiplexer/demultiplexer module and associated methods

Electro-optical interface module and associated methods

Thermal management system for multi-chip-module and associated methods

Laser module for optical data communication system within silicon interposer

Apparatus for optical fiber-to-photonic chip connection and associated methods

Pooled memory system enabled by monolithic in-package optical I/O

Photonics systems to enable top-side wafer-level optical and electrical test

Retro reflector and associated methods

Chip-last wafer-level fan-out with optical fiber alignment structure

Apparatus for optical fiber-to-photonic chip connection and associated methods

Thermal management system for multi-chip-module and associated methods

Beam steering structure with integrated polarization splitter

Chip-to-chip optical data communication system

Chip-last wafer-level fan-out with optical fiber alignment structure

Laser module for optical data communication system within silicon interposer

Electro-optical interface module and associated methods

Thermal management system for multi-chip-module and associated methods

Laser module for optical data communication system

TORminator system and associated methods

Laser module for optical data communication system within silicon interposer

Beam steering structure with integrated polarization splitter

Chip-to-chip optical data communication system

Optical multiplexer/demultiplexer module and associated methods

Pooled memory system enabled by monolithic in-package optical I/O

Fiber attach enabled wafer level fanout

Multi-chip packaging of silicon photonics

Remote memory architectures enabled by monolithic in-package optical i/o

Fiber attach enabled wafer level fanout

Wafer-level handle replacement processing

Systems and methods for wafer-level photonic testing

Photonic systems to enable top-side wafer-level optical and electrical test

Systems and methods for wafer-level photonic testing

Planar fiber shuffle

Wafer-level handle replacement

Laser module for optical data communication system

Low-power optical input/output chiplet for ethernet switches (TeraPHYe)

Lens assembly for optical fiber coupling to target and associated methods

Beam turning assembly with polarization splitter