Inventor
GULER LEONARD
US16 patents
Patents
16 patentsUS11342411B2May 24, 2022
Cavity spacer for nanowire transistors
INTEL CORP7 citations84
US12002810B2Jun 4, 2024
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach
INTEL CORP5 citations74
US11929396B2Mar 12, 2024
Cavity spacer for nanowire transistors
INTEL CORP2 citations72
US11404578B2Aug 2, 2022
Dielectric isolation layer between a nanowire transistor and a substrate
INTEL CORP3 citations72
US11189614B2Nov 30, 2021
Process etch with reduced loading effect
INTEL CORP2 citations71
US11569231B2Jan 31, 2023
Non-planar transistors with channel regions having varying widths
INTEL CORP3 citations69
US12426316B2Sep 23, 2025
Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material
INTEL CORP0 citations62
US12369393B2Jul 22, 2025
Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach
INTEL CORP0 citations62
US11538937B2Dec 27, 2022
Fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material
INTEL CORP0 citations62
US12349394B2Jul 1, 2025
Dielectric isolation layer between a nanowire transistor and a substrate
INTEL CORP0 citations61
US12328905B2Jun 10, 2025
Cavity spacer for nanowire transistors
INTEL CORP0 citations61
US11901458B2Feb 13, 2024
Dielectric isolation layer between a nanowire transistor and a substrate
INTEL CORP0 citations61
US12484207B2Nov 25, 2025
SRAM with channel count contrast for greater read stability
INTEL CORP0 citations59
US12131991B2Oct 29, 2024
Self aligned gratings for tight pitch interconnects and methods of fabrication
INTEL CORP0 citations58
US11251117B2Feb 15, 2022
Self aligned gratings for tight pitch interconnects and methods of fabrication
INTEL CORP0 citations58
US12405526B2Sep 2, 2025
Extreme ultraviolet lithography patterning with assist features
INTEL CORP0 citations39