Inventor
RAGHURAM USHA
US32 patents
⚠️ This page may combine multiple inventors who share the name “RAGHURAM USHA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SANDISK 3D LLC
13 patentsUS7915164B2Mar 29, 2011
Method for forming doped polysilicon via connecting polysilicon layers
SANDISK 3D LLC251 citations99
US7566974B2Jul 28, 2009
Doped polysilicon via connecting polysilicon layers
SANDISK 3D LLC190 citations99
US7575984B2Aug 18, 2009
Conductive hard mask to protect patterned features during trench etch
SANDISK 3D LLC111 citations97
US7307013B2Dec 11, 2007
Nonselective unpatterned etchback to expose buried patterned features
SANDISK 3D LLC67 citations97
US7906392B2Mar 15, 2011
Pillar devices and methods of making thereof
SANDISK 3D LLC21 citations92
US7517796B2Apr 14, 2009
Method for patterning submicron pillars
SANDISK 3D LLC22 citations92
US7422985B2Sep 9, 2008
Method for reducing dielectric overetch using a dielectric etch stop at a planar surface
SANDISK 3D LLC16 citations92
US8008187B2Aug 30, 2011
Method for reducing dielectric overetch using a dielectric etch stop at a planar surface
SANDISK 3D LLC7 citations84
US7846782B2Dec 7, 2010
Diode array and method of making thereof
SANDISK 3D LLC13 citations83
US7915163B2Mar 29, 2011
Method for forming doped polysilicon via connecting polysilicon layers
SANDISK 3D LLC4 citations74
US7790607B2Sep 7, 2010
Method for reducing dielectric overetch using a dielectric etch stop at a planar surface
SANDISK 3D LLC1 citations63
US7955515B2Jun 7, 2011
Method of plasma etching transition metal oxides
SANDISK 3D LLC2 citations62
US8722518B2May 13, 2014
Methods for protecting patterned features during trench etch
SANDISK 3D LLC0 citations52
CYPRESS SEMICONDUCTOR CORP
4 patentsUS6756315B1Jun 29, 2004
Method of forming contact openings
CYPRESS SEMICONDUCTOR CORP7 citations74
US6406640B1Jun 18, 2002
Plasma etching method
CYPRESS SEMICONDUCTOR CORP9 citations70
US6165375ADec 26, 2000
Plasma etching method
CYPRESS SEMICONDUCTOR CORP12 citations70
US6890860B1May 10, 2005
Method for etching and/or patterning a silicon-containing layer
CYPRESS SEMICONDUCTOR CORP0 citations49
RAGHURAM USHA
3 patentsUS8163593B2Apr 24, 2012
Method of making a nonvolatile phase change memory cell having a reduced contact area
RAGHURAM USHA8 citations83
US8298931B2Oct 30, 2012
Dual damascene with amorphous carbon for 3D deep via/trench application
RAGHURAM USHA12 citations82
US8759176B2Jun 24, 2014
Patterning of submicron pillars in a memory array
RAGHURAM USHA0 citations50
GLOBALFOUNDRIES INC
2 patentsJOSHI AMOL
2 patentsUS8735302B2May 27, 2014
High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction
JOSHI AMOL4 citations70
US8854067B2Oct 7, 2014
Circular transmission line methods compatible with combinatorial processing of semiconductors
JOSHI AMOL1 citations48