Inventor

AGARWAL ANANT

US134 patents

⚠️ This page may combine multiple inventors who share the name “AGARWAL ANANT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AGARWAL ANANT

TILERA CORP

Managing cache memory in a parallel processing environment

Managing memory access in a parallel processing environment

Pattern matching in a multiprocessor environment with finite state automaton transitions based on an order of vectors in a state transition table

Caching in multicore and multiprocessor architectures

Managing data forwarded between processors in a parallel processing environment based on operations associated with instructions issued by the processors

Coupling data in a parallel processing environment

Mapping memory in a parallel processing environment

Managing data in a parallel processing environment

Coupling integrated circuits in a parallel processing environment

Managing set associative cache memory according to entry type

Caching in multicore and multiprocessor architectures

Caching in multicore and multiprocessor architectures

Caching in multicore and multiprocessor architectures

Directing data in a parallel processing environment

Protection in a parallel processing environment using access information associated with each switch to prevent data from being forwarded outside a plurality of tiles

Managing memory in a parallel processing environment

MASSACHUSETTS INST TECHNOLOGY

Managing yield for a parallel processing integrated circuit

Configuring sets of processor cores for processing instructions

Managing power in a parallel processing environment

Configuring circuitry in a parallel processing environment

Transferring data in a parallel processing environment

Virtual interconnections for reconfigurable logic systems

Virtual interconnections for reconfigurable logic systems

Cache memory system and method with multiple hashing functions and hash control storage

Distributing computations in a parallel processing environment

Transferring data in a parallel processing environment

Virtual architectures in a parallel processing environment

CREE INC

Semiconductor devices including schottky diodes with controlled breakdown

Methods of processing semiconductor wafers having silicon carbide power devices thereon

Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel

Transistor with A-face conductive channel and trench protecting well region

AGARWAL ANANT

Processing data in a parallel processing environment

Architecture and programming in a parallel processing environment with switch-interconnected processors

Transferring data in a parallel processing environment

INCERT SOFTWARE CORP

Method for back tracing program execution

Test, protection, and repair through binary code augmentation

Test protection, and repair through binary-code augmentation

LEE WALTER

Compiling code for parallel processing architectures based on control flow

Memory access assignment for parallel processing architectures

Distributing parallelism for parallel processing architectures

GRIFFIN PATRICK ROBERT

Programming in a multiprocessor environment

Computing in parallel processing environments

VIRTUAL MACHINE WORKS INC

Pipe lined static router and scheduler for configurable logic system performing simultaneous communications and computation

Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation

MELLANOX TECHNOLOGIES LTD

Computing in parallel processing environments

WENTZLAFF DAVID M

Transferring and storing data in multicore and multiprocessor architectures

WENTZLAFF DAVID

Managing data provided to switches in a parallel processing environment

VERITAS OPERATING CORP

Method for simulating back program execution from a traceback sequence

IKOS SYSTEMS INC

Circuit partitioning technique for use with multiplexed inter-connections

BRATT IAN RUDOLF

Caching in multicore and multiprocessor architectures