Inventor

MATTINA MATTHEW

US58 patents

⚠️ This page may combine multiple inventors who share the name “MATTINA MATTHEW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MATTINA MATTHEW

ADVANCED RISC MACH LTD

System, method and apparatus for training neural networks using multiple datasets

Hardware accelerator for IM2COL operation

Apparatus and method for matrix operations

Systolic convolutional neural network

Matrix multiplication system and method

Mixed-precision computation unit

Processor for sparse matrix computation

Hybrid filter banks for artificial neural networks

Non-volatile memory-based compact mixed-signal multiply-accumulate engine

Artificial neural network optical hardware accelerator

Time domain unrolling sparse matrix multiplication system and method

Multi-dimensional data path architecture

TILERA CORP

Managing cache memory in a parallel processing environment

Caching in multicore and multiprocessor architectures

Managing memory access in a parallel processing environment

Mapping memory in a parallel processing environment

Managing set associative cache memory according to entry type

Caching in multicore and multiprocessor architectures

Caching in multicore and multiprocessor architectures

Caching in multicore and multiprocessor architectures

Caching in multicore and multiprocessor architectures

High performance, scalable multi chip interconnect

BRATT IAN RUDOLF

Condensed router headers with low latency output port calculation

Caching in multicore and multiprocessor architectures

Low latency dynamic route selection

Route prediction in packet switched networks

Route prediction in packet switched networks

Low latency dynamic route selection

MELLANOX TECHNOLOGIES LTD

Computing in parallel processing environments

Computing in parallel processing environments

Computing in parallel processing environments

High performance, scalable multi chip interconnect

Cache coherency in multiprocessor system

High performance, scalable multi chip interconnect

INTEL CORP

Flow control method and apparatus for single packet arrival on a bidirectional ring interconnect

Apparatus and method for partitioning a shared cache of a chip multi-processor

Method and apparatus for preventing starvation in a slotted-ring network

Predictive early write-back of owned cache blocks in a shared memory computer system

AGARWAL ANANT

Caching in multicore and multiprocessor architectures

Caching in multicore and multiprocessor architectures

Caching in multicore and multiprocessor architectures

Caching in multicore and multiprocessor architectures

MATTINA MATTHEW

Managing cache memory in a parallel processing environment

Global socket to socket cache coherence architecture

Managing cache memory in a parallel processing environment

WENTZLAFF DAVID M

Transferring and storing data in multicore and multiprocessor architectures

Managing cache memory in a parallel processing environment

GRIFFIN PATRICK ROBERT

Computing in parallel processing environments

CARLSON ANDREW

Multi-core processor using three dimensional integration

WENTZLAFF DAVID

Managing cache memory in a parallel processing environment