Inventor
SHARMA MADHUMITRA
US18 patents
⚠️ This page may combine multiple inventors who share the name “SHARMA MADHUMITRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
COMPAQ COMPUTER CORP
12 patentsUS6108737AAug 22, 2000
Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system
COMPAQ COMPUTER CORP148 citations99
US6055605AApr 25, 2000
Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches
COMPAQ COMPUTER CORP181 citations99
US6209065B1Mar 27, 2001
Mechanism for optimizing generation of commit-signals in a distributed shared-memory system
COMPAQ COMPUTER CORP144 citations98
US6101420AAug 8, 2000
Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories
COMPAQ COMPUTER CORP90 citations97
US6085263AJul 4, 2000
Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor
COMPAQ COMPUTER CORP111 citations97
US6286090B1Sep 4, 2001
Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches
COMPAQ COMPUTER CORP66 citations96
US6094686AJul 25, 2000
Multi-processor system for transferring data without incurring deadlock using hierarchical virtual channels
COMPAQ COMPUTER CORP73 citations96
US6279084B1Aug 21, 2001
Shadow commands to optimize sequencing of requests in a switch-based multi-processor system
COMPAQ COMPUTER CORP96 citations95
US6154816ANov 28, 2000
Low occupancy protocol for managing concurrent transactions with dependencies
COMPAQ COMPUTER CORP78 citations95
US6249520B1Jun 19, 2001
High-performance non-blocking switch with multiple channel ordering constraints
COMPAQ COMPUTER CORP63 citations94
US6202126B1Mar 13, 2001
Victimization of clean data blocks
COMPAQ COMPUTER CORP30 citations92
US6122714ASep 19, 2000
Order supporting mechanisms for use in a switch-based multi-processor system
COMPAQ COMPUTER CORP42 citations92
HEWLETT PACKARD DEVELOPMENT CO
3 patentsUS6801986B2Oct 5, 2004
Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation
HEWLETT PACKARD DEVELOPMENT CO37 citations92
US6961825B2Nov 1, 2005
Cache coherency mechanism using arbitration masks
HEWLETT PACKARD DEVELOPMENT CO5 citations62
US6904465B2Jun 7, 2005
Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch
HEWLETT PACKARD DEVELOPMENT CO1 citations52