Inventor

NAZARIAN HAGOP

US116 patents

⚠️ This page may combine multiple inventors who share the name “NAZARIAN HAGOP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAZARIAN HAGOP

CROSSBAR INC

Field programmable gate array utilizing two-terminal non-volatile memory

Disturb-resistant non-volatile memory device and method

Two-terminal memory compatibility with NAND flash memory set features type mechanisms

ReRAM based NAND like architecture with configurable page size

Switching device having a non-linear element

Circuit for concurrent read operation and method therefor

Read operation with data latch and signal termination for 1TNR memory array

Capacitive discharge programming for two-terminal memory cells

Neuromorphic logic for an array of high on/off ratio non-volatile memory cells

Switching block configuration bit comprising a non-volatile memory cell

4F2 resistive non-volatile memory formed in a NAND architecture

Switching block configuration bit comprising a non-volatile memory cell

Selector-based non-volatile cell fabrication utilizing IC-foundry compatible process

Programmable logic applications for an array of high on/off ratio and high speed non-volatile memory cells

Memory array architecture with two-terminal memory cells

Resistive RAM with preferental filament formation region and methods

Memory array with embedded source line driver and improved voltage regularity

Resistive memory cell with solid state diode

Field programmable gate array utilizing two-terminal non-volatile memory

Resistive random access memory equalization and sensing

Interface control for improved switching in RRAM

State change detection for two-terminal memory during application of a state-changing stimulus

Sensing a non-volatile memory device utilizing selector device holding characteristics

Differential programming of two-terminal memory with intrinsic error suppression and wordline coupling

Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement

Methods and apparatus for facilitated program and erase of two-terminal memory devices

Method for fabricating an array of 4F2 resistive non-volatile memory in a NAND architecture

Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor

Read operation with data latch and signal termination for 1TNR memory array

NAZARIAN HAGOP

NAND architecture having a resistive memory cell connected to a control gate of a field-effect transistor

Write and erase scheme for resistive memory device

Non-volatile variable capacitive device including resistive memory cell

Memory array architecture with two-terminal memory cells

Field programmable gate array utilizing two-terminal non-volatile memory

Field programmable gate array utilizing two-terminal non-volatile memory

Re-configurable mixed-mode integrated circuit architecture

Error correction for flash memory

CYPRESS SEMICONDUCTOR CORP

High speed configuration independent programmable macrocell

Slew rate control circuit for an integrated circuit

OR array architecture for a programmable logic device

High-speed ratio CMOS logic structure with static and dynamic pullups and/or pulldowns using feedback

JO SUNG HYUN

Interface control for improved switching in RRAM

Integration of an amorphous silicon resistive switching device

SPANSION LLC

Nonvolatile memory array architecture

Reading multi-cell memory devices utilizing complementary bit information

NGUYEN SANG

High operating speed resistive random access memory

KUO HARRY

Circuit for concurrent read operation and method therefor

INFORMATION STORAGE DEVICES

Method and apparatus for reducing power supply current surges in a charge pump using a delayed clock line

GEE HARRY

Three dimension programmable resistive random accessed memory array with shared bitline and method

HERNER SCOTT BRAD

Disturb-resistant non-volatile memory device and method