Inventor

KAMAL TAZRIEN

US42 patents

⚠️ This page may combine multiple inventors who share the name “KAMAL TAZRIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAMAL TAZRIEN

ADVANCED MICRO DEVICES INC

Bitline hard mask spacer flow for memory cell scaling

Semiconductor memory with deuterated materials

Source drain implant during ONO formation for improved isolation of SONOS devices

Disposable hard mask for memory bitline scaling

Memory device having A P+ gate and thin bottom oxide and method of erasing same

Flash memory with controlled wordline width

Charge-trapping memory arrays resistant to damage from contact hole information

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL

Structure and method for preventing UV radiation damage and increasing data retention in memory cells

Memory manufacturing process using bitline rapid thermal anneal

Memory wordline hard mask

Method of making memory wordline hard mask extension

Hard mask spacer for sublithographic bitline

Narrow bitline using Safier for mirrorbit

PECVD silicon-rich oxide layer for reduced UV charging

Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance

Memory wordline spacer

Memory with disposable ARC for wordline formation

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing

Memory manufacturing process using disposable ARC for wordline formation

Hard mask process for memory device without bitline shorts

Memory device having a P+ gate and thin bottom oxide and method of erasing same

Undoped oxide liner/BPSG for improved data retention

Memory wordline spacer

FASL LLC

Memory device having high work function gate and method of erasing same

ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices

ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device

ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices

Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen

Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device

Method of manufacturing a semiconductor memory with deuterated materials

Liner for semiconductor memories and manufacturing method therefor

SPANSION LLC

Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device

LDC implant for mirrorbit to improve Vt roll-off and form sharper junction

Method for forming bit lines for semiconductor devices

Semiconductor memory with data retention liner

Method for forming bit lines for semiconductor devices

Method and apparatus for protection against process-induced charging

GEORGIA TECH RES INST

Method of stripping photoresist using alcohols

ROGERS DAVID M

Method and apparatus for protection against process-induced charging

RAMSBEY MARK T

Memory manufacturing process with bitline isolation