Inventor
KHARE MANOJ
US18 patents
⚠️ This page may combine multiple inventors who share the name “KHARE MANOJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
16 patentsUS6487643B1Nov 26, 2002
Method and apparatus for preventing starvation in a multi-node architecture
INTEL CORP83 citations98
US6971098B2Nov 29, 2005
Method and apparatus for managing transaction requests in a multi-node architecture
INTEL CORP88 citations97
US6810467B1Oct 26, 2004
Method and apparatus for centralized snoop filtering
INTEL CORP72 citations97
US6615319B2Sep 2, 2003
Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture
INTEL CORP95 citations97
US7234029B2Jun 19, 2007
Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
INTEL CORP27 citations92
US7124252B1Oct 17, 2006
Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system
INTEL CORP28 citations92
US6842830B2Jan 11, 2005
Mechanism for handling explicit writeback in a cache coherent multi-node architecture
INTEL CORP39 citations92
US6772298B2Aug 3, 2004
Method and apparatus for invalidating a cache line without data return in a multi-node architecture
INTEL CORP24 citations92
US6209072B1Mar 27, 2001
Source synchronous interface between master and slave using a deskew latch
INTEL CORP27 citations88
US6859864B2Feb 22, 2005
Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line
INTEL CORP14 citations84
US7996625B2Aug 9, 2011
Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
INTEL CORP10 citations83
US7167957B2Jan 23, 2007
Mechanism for handling explicit writeback in a cache coherent multi-node architecture
INTEL CORP9 citations73
US5367657ANov 22, 1994
Method and apparatus for efficient read prefetching of instruction code data in computer memory subsystems
INTEL CORP19 citations73
US6826619B1Nov 30, 2004
Method and apparatus for preventing starvation in a multi-node architecture
INTEL CORP11 citations72
US6976129B2Dec 13, 2005
Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture
INTEL CORP5 citations63
US6622215B2Sep 16, 2003
Mechanism for handling conflicts in a multi-node computer architecture
INTEL CORP4 citations62
CISCO TECH INC
2 patentsUS7464254B2Dec 9, 2008
Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data
CISCO TECH INC77 citations96
US7085918B2Aug 1, 2006
Methods and apparatuses for evaluation of regular expressions of arbitrary size
CISCO TECH INC32 citations91