Inventor
SAXENA NIRMAL RAJ
US19 patents
⚠️ This page may combine multiple inventors who share the name “SAXENA NIRMAL RAJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INPHI CORP
8 patentsUS9430437B1Aug 30, 2016
PCIE lane aggregation over a high speed link
INPHI CORP25 citations93
US9348539B1May 24, 2016
Memory centric computing
INPHI CORP43 citations93
US8996960B1Mar 31, 2015
Vertical error correction code for DRAM memory
INPHI CORP24 citations92
US9846669B2Dec 19, 2017
PCIe lane aggregation over a high speed link
INPHI CORP4 citations83
US9250831B1Feb 2, 2016
Isolated shared memory architecture (iSMA)
INPHI CORP3 citations73
US10929325B2Feb 23, 2021
PCIE lane aggregation over a high speed link
INPHI CORP1 citations72
US10572425B2Feb 25, 2020
PCIe lane aggregation over a high speed link
INPHI CORP1 citations72
US10235318B2Mar 19, 2019
PCIe lane aggregation over a high speed link
INPHI CORP3 citations72
NVIDIA CORP
7 patentsUS8037391B1Oct 11, 2011
Raid-6 computation system and method
NVIDIA CORP40 citations92
US9348762B2May 24, 2016
Technique for accessing content-addressable memory
NVIDIA CORP9 citations83
US8984372B2Mar 17, 2015
Techniques for storing ECC checkbits in a level two cache
NVIDIA CORP8 citations83
US11720440B2Aug 8, 2023
Error containment for enabling local checkpoint and recovery
NVIDIA CORP1 citations56
US9720858B2Aug 1, 2017
Technique for performing memory access operations via texture hardware
NVIDIA CORP0 citations51
US11874742B2Jan 16, 2024
Techniques for recovering from errors when executing software applications on parallel processors
NVIDIA CORP0 citations44
US9697006B2Jul 4, 2017
Technique for performing memory access operations via texture hardware
NVIDIA CORP0 citations41