Inventor

STRACHAN ANDREW

US17 patents

⚠️ This page may combine multiple inventors who share the name “STRACHAN ANDREW”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STRACHAN ANDREW

NAT SEMICONDUCTOR CORP

PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in and method for designing and manufacturing such device

Integration of trench power transistors into a 1.5 μm BCD process

LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability

Layout optimization of integrated trench VDMOS arrays

Low cost, high density diffusion diode-capacitor

Method of improving the breakdown voltage of a diffused semiconductor junction

Method of forming a MIM capacitor

Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in

EEPROM structure with improved data retention utilizing biased metal plate and conductive layer exclusion

Method of forming contact to poly-filled trench isolation region

RAGHAVAN VENKAT

Method for integrating MIM capacitor and thin film resistor in modular two layer metal process and corresponding device

Method of forming a robust, modular MIS (metal-insulator-semiconductor) capacitor with improved capacitance density

Data retention in a single poly EPROM cell

TEXAS INSTRUMENTS INC

Vertically-constructed, temperature-sensing resistors and methods of making the same

Vertically-constructed, temperature-sensing resistors and methods of making the same

Dynamic biasing to mitigate electrical stress in integrated resistors

BRISBIN DOUGLAS

Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in