Inventor
JUCHMES WERNER
DE9 patents
⚠️ This page may combine multiple inventors who share the name “JUCHMES WERNER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
8 patentsUS9431096B1Aug 30, 2016
Hierarchical negative bitline boost write assist for SRAM memory devices
IBM10 citations82
US7844871B2Nov 30, 2010
Test interface for memory elements
IBM6 citations61
US11043938B2Jun 22, 2021
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature
IBM0 citations60
US10984160B1Apr 20, 2021
Analysis and modification of circuit designs
IBM0 citations57
US7558138B1Jul 7, 2009
Bypass circuit for memory arrays
IBM4 citations53
US10587248B2Mar 10, 2020
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature
IBM0 citations50
US10367481B2Jul 30, 2019
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature
IBM0 citations50
US9666278B2May 30, 2017
Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell block
IBM0 citations39