Inventor
HARLEY ERIC C
US18 patents
⚠️ This page may combine multiple inventors who share the name “HARLEY ERIC C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
11 patentsUS9123826B1Sep 1, 2015
Single crystal source-drain merged by polycrystalline material
IBM8 citations84
US10243077B2Mar 26, 2019
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
IBM2 citations73
US9917190B2Mar 13, 2018
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
IBM2 citations73
US9312364B2Apr 12, 2016
finFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
IBM3 citations73
US9412843B2Aug 9, 2016
Method for embedded diamond-shaped stress element
IBM4 citations72
US7769134B1Aug 3, 2010
Measuring strain of epitaxial films using micro x-ray diffraction for in-line metrology
IBM7 citations72
US11081583B2Aug 3, 2021
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
IBM0 citations62
US8987093B2Mar 24, 2015
Multigate finFETs with epitaxially-grown merged source/drains
IBM2 citations62
US8618617B2Dec 31, 2013
Field effect transistor device
IBM3 citations62
US10615279B2Apr 7, 2020
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
IBM0 citations52
US9752251B2Sep 5, 2017
Self-limiting selective epitaxy process for preventing merger of semiconductor fins
IBM1 citations50
GLOBALFOUNDRIES INC
5 patentsUS9577100B2Feb 21, 2017
FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions
GLOBALFOUNDRIES INC17 citations84
US9246003B2Jan 26, 2016
FINFET structures with fins recessed beneath the gate
GLOBALFOUNDRIES INC7 citations84
US9236477B2Jan 12, 2016
Graphene transistor with a sublithographic channel width
GLOBALFOUNDRIES INC2 citations62
US9219114B2Dec 22, 2015
Partial FIN on oxide for improved electrical isolation of raised active regions
GLOBALFOUNDRIES INC1 citations52
US9390884B2Jul 12, 2016
Method of inspecting a semiconductor substrate
GLOBALFOUNDRIES INC0 citations50