Inventor
STOKER MATTHEW W
US21 patents
⚠️ This page may combine multiple inventors who share the name “STOKER MATTHEW W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
GLOBALFOUNDRIES INC
7 patentsUS10396078B2Aug 27, 2019
Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same
GLOBALFOUNDRIES INC9 citations82
US10020307B1Jul 10, 2018
Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming same
GLOBALFOUNDRIES INC9 citations82
US9673295B2Jun 6, 2017
Contact resistance optimization via EPI growth engineering
GLOBALFOUNDRIES INC3 citations71
US10204984B1Feb 12, 2019
Methods, apparatus and system for forming increased surface regions within EPI structures for improved trench silicide
GLOBALFOUNDRIES INC3 citations70
US9236477B2Jan 12, 2016
Graphene transistor with a sublithographic channel width
GLOBALFOUNDRIES INC2 citations62
US10121706B2Nov 6, 2018
Semiconductor structure including two-dimensional and three-dimensional bonding materials
GLOBALFOUNDRIES INC0 citations46
US10529831B1Jan 7, 2020
Methods, apparatus, and system for forming epitaxial formations with reduced risk of merging
GLOBALFOUNDRIES INC0 citations41
IBM
6 patentsUS9190406B2Nov 17, 2015
Fin field effect transistors having heteroepitaxial channels
IBM7 citations84
US8940595B2Jan 27, 2015
Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
IBM8 citations84
US8361859B2Jan 29, 2013
Stressed transistor with improved metastability
IBM13 citations84
US9287399B2Mar 15, 2016
Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
IBM5 citations72
US8618617B2Dec 31, 2013
Field effect transistor device
IBM3 citations62
US8779525B2Jul 15, 2014
Method for growing strain-inducing materials in CMOS circuits in a gate first flow
IBM0 citations51
FREESCALE SEMICONDUCTOR INC
5 patentsUS7238580B2Jul 3, 2007
Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration
FREESCALE SEMICONDUCTOR INC59 citations97
US7029980B2Apr 18, 2006
Method of manufacturing SOI template layer
FREESCALE SEMICONDUCTOR INC25 citations92
US7928502B2Apr 19, 2011
Transistor devices with nano-crystal gate structures
FREESCALE SEMICONDUCTOR INC2 citations62
US7700438B2Apr 20, 2010
MOS device with nano-crystal gate structure
FREESCALE SEMICONDUCTOR INC5 citations62
US7683443B2Mar 23, 2010
MOS devices with multi-layer gate stack
FREESCALE SEMICONDUCTOR INC0 citations52