Inventor

BUNCE PAUL A

US34 patents

⚠️ This page may combine multiple inventors who share the name “BUNCE PAUL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BUNCE PAUL A

IBM

Write control circuitry and method for a memory array configured with multiple memory subarrays

Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays

Memory output timing control circuit with merged functions

Write driver circuit for memory array

Write control circuitry and method for a memory array configured with multiple memory subarrays

SOI cell stability test method

Split voltage level restore and evaluate clock signals for memory address decoding

Method and apparatus for address generation

Programmable analog control of a bitline evaluation circuit

System and method for synchronizing memory array signals

Method for skip over redundancy decode with very low overhead

High speed latch and compare function

System for implementing a column redundancy scheme for arrays with controls that span multiple data bits

SRAM supply voltage global bitline precharge pulse

Write control method for a memory array configured with multiple memory subarrays

Clock control method and apparatus for a memory array

Internal bypassing of memory array devices

Integrated system logic and ABIST data compression for an SRAM directory

Method for enabling scan of defective ram prior to repair

Write/read priority blocking scheme using parallel static address decode path

Write/read priority blocking scheme using parallel static address decode path

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

Cache array with reduced power consumption

Cache array with reduced power consumption

Managing semiconductor memory array leakage current

Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservation

Managing semiconductor memory array leakage current

Increasing memory operating frequency

Jam latch for latching memory array output data

Incorporating bit write capability with column interleave write enable and column redundancy steering

Circuit and method for writing a binary value to a memory cell

High frequency write through memory device

BUNCE PAUL A

Port enable signal generation for gating a memory array device output

Programmable control clock circuit including scan mode