Inventor

SHEARER ROBERT ALLEN

US49 patents

⚠️ This page may combine multiple inventors who share the name “SHEARER ROBERT ALLEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHEARER ROBERT ALLEN

IBM

Method for reducing network bandwidth by delaying shadow ray generation

Generating efficient spatial indexes for predictably dynamic objects

Method for improving spatial index efficiency by jittering splitting planes

Efficient and flexible data organization for acceleration data structure nodes

Deferred acceleration data structure optimization for improved performance

Dynamically configuring and selecting multiple ray tracing intersection methods

Combined spatial index for static and dynamic objects within a three-dimensional scene

Dynamically load balancing game physics using real-time object scaling

Image processing with highly threaded texture fragment generation

Updating ray traced acceleration data structures between frames based on changing perspective

Method and apparatus for memory utilization

Dynamic reallocation of processing cores for balanced ray tracing graphics workload

Dynamic determination of optimal spatial index mapping to processor thread resources

Method and apparatus for communicating between threads

Apparatus and method for efficient transmission of unaligned data

Processing unit incorporating instruction-based persistent vector multiplexer control

Processing unit incorporating special purpose register for use with instruction-based persistent vector multiplexer control

Methods and systems for reducing the number of rays passed between processing elements in a distributed ray tracing system

Reallocation of spatial index traversal between processing elements in response to changes in ray tracing graphics workload

Clock frequency detect with programmable jitter tolerance

MICROSOFT TECHNOLOGY LICENSING LLC

Prioritized sequencing of device inrush current

Low power DMA snoop and skip

Interrupt controller

Low-latency timing control

Expected lifetime management

Adaptive power down of intra-chip interconnect

Serial lookup of tag ways

Adaptive power down of intra-chip interconnect

Control of predication across clock domains

Low power DMA labeling

Cache memory with reduced power consumption mode

Serial tag lookup with way-prediction

Power aware hash function for cache memory mapping

MEJDRICH ERIC OLIVER

Efficient texture processing of pixel groups with SIMD execution unit

Tree insertion depth adjustment based on view frustum and distance culling

Tree insertion depth adjustment based on view frustum and distance culling

Streaming physics collision detection in multithreaded rendering software pipeline

Rolling context data structure for maintaining state data in a multithreaded image processing pipeline

User-defined non-visible geometry featuring ray filtering

SHEARER ROBERT ALLEN

Utilizing ray tracing for enhanced artificial intelligence path-finding

Using ray tracing for real time audio synthesis

Methods and systems for partitioning a spatial index

BROWN JEFFREY DOUGLAS

Cooperative utilization of spatial indices between application and rendering hardware

Dynamic spatial index remapping for optimal aggregate performance

FOWLER DAVID KEITH

Resetting of dynamically grown accelerated data structure

Box casting using an integrated acceleration data structure

KUPFERSCHMIDT MARK GARY

Two-tiered dynamic load balancing using sets of distributed thread pools

FOWLER DAVE

Hybrid rendering of image data utilizing streaming geometry frontend interconnected to physical rendering backend through dynamic accelerated data structure generator

HOOVER RUSSELL DEAN

Rendering of stereoscopic images with multithreaded rendering software pipeline