Inventor

TAN ELLIOT N

US25 patents

⚠️ This page may combine multiple inventors who share the name “TAN ELLIOT N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAN ELLIOT N

INTEL CORP

Advanced lithography and self-assembled devices

Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects

Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects

Pattern decomposition lithography techniques

Advanced lithography and self-assembled devices

Advanced lithography and self-assembled devices

Advanced lithography and self-assembled devices

Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects

Method and structure to contact tight pitch conductive layers with guided vias

Methods for forming interconnect layers having tight pitch interconnect structures

Pattern decomposition lithography techniques

Pattern decomposition lithography techniques

Pattern decomposition lithography techniques

Vertical edge blocking (VEB) technique for increasing patterning process margin

Thin film transistors having a backside channel contact for high density memory

Fabrication of thin film fin transistor structure

Vertical edge blocking (VEB) technique for increasing patterning process margin

Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects

Multilevel wordline assembly for embedded DRAM

Memory architecture with shared bitline at back-end-of-line

Integrated circuit structures having cut metal gates with dielectric spacer fill

Preformed interlayer connections for integrated circuit devices

WALLACE CHARLES H

Pattern decomposition lithography techniques

TAN ELLIOT N

Feature size reduction

SIVAKUMAR SWAMINATHAN

Spacer assisted pitch division lithography