Inventor

NYHUS PAUL A

US45 patents

⚠️ This page may combine multiple inventors who share the name “NYHUS PAUL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NYHUS PAUL A

INTEL CORP

Self-aligned via and plug patterning for back end of line (BEOL) interconnects

Sub-resolution assist features

Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects

Advanced lithography and self-assembled devices

Patterning of vertical nanowire transistor channel and gate with directed self assembly

Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects

Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects

Pre-patterned hard mask for ultrafast lithographic imaging

Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures

Advanced lithography and self-assembled devices

Advanced lithography and self-assembled devices

Advanced lithography and self-assembled devices

Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication and structures resulting therefrom

Self-aligned via and plug patterning for back end of line (BEOL) interconnects

Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects

Self-aligned via and plug patterning for back end of line (BEOL) interconnects

Patterning of vertical nanowire transistor channel and gate with directed self assembly

Patterning of vertical nanowire transistor channel and gate with directed self assembly

Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication

Contact over active gate structures with conductive trench contact taps for advanced integrated circuit structure fabrication

Colored gratings in microelectronic structures

Contact over active gate structures with metal oxide layers to inhibit shorting

Materials and layout design options for DSA on transition regions over active die

Via and plug architectures for integrated circuit interconnects and methods of manufacture

Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging

Vertical edge blocking (VEB) technique for increasing patterning process margin

Vertical edge blocking (VEB) technique for increasing patterning process margin

Sub-resolution assist features

Contact over active gate structures using directed self-assembly for advanced integrated circuit structure fabrication

Directed self-assembly enabled subtractive metal patterning

Gate spacing in integrated circuit structures

Guard ring structure for an integrated circuit

Conductive cap-based approaches for conductive via fabrication and structures resulting therefrom

Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnects

Patterning of vertical nanowire transistor channel and gate with directed self assembly

Pre-patterned hard mask for ultrafast lithographic imaging

Vertical metal splitting using helmets and wrap-around dielectric spacers

Underlying absorbing or conducting layer for Ebeam direct write (EBDW) lithography

Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures

Directed self-assembly enabled patterning over metal layers using assisting features

NYHUS PAUL A

Patterning of vertical nanowire transistor channel and gate with directed self assembly

Directed self assembly of block copolymers to form vias aligned with interconnects

Directed self assembly of block copolymers to form vias aligned with interconnects

Exposure activated chemically amplified directed self-assembly (DSA) for back end of line (BEOL) pattern cutting and plugging

Techniques for phase tuning for process optimization