Inventor

ROSE ANDREW CHRISTOPHER

GB46 patents

⚠️ This page may combine multiple inventors who share the name “ROSE ANDREW CHRISTOPHER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROSE ANDREW CHRISTOPHER

ADVANCED RISC MACH LTD

Data processing system having an external instruction set and an internal instruction set

Handling of conditional instructions in a data processing apparatus

Data processing apparatus and method for moving data elements between specified registers and a continuous block of memory

Program instruction interpretation

Restarting translated instructions

Storing stack operands in registers

Debugging data processing systems

Table lookup operation within a data processing system

Data processing apparatus and method for moving data elements between a chosen lane of parallel processing in registers and a structure within memory

Null exception handling

Data processing apparatus and method for merging secure and non-secure data into an output data stream

Cache power management

Data processing apparatus and method for handling instructions to be executed by processing circuitry

Decoder for generating N output signals from two or more precharged input signals

Apparatus and method including an ownership table for indicating owner processes for blocks of physical addresses of a memory

Apparatus and method for address translation and control of whether an access request is rejected based on an ownership table indicating an owner process for a block of physical addresses

Protected exception handling

Secure initialisation

Allocation of branch target cache resources in dependence upon program instructions within an instruction queue

Invalidating stored address translations

Instruction pre-decoding of multiple instruction sets

Data processing apparatus and method for handling instructions to be executed by processing circuitry

Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a start address

Unhandled operation handling in multiple instruction set systems

Synchronisation of signals between asynchronous logic

Data processing apparatus and method for performing hazard detection

Apparatus and method for handling data in a cache

Apparatus and method for sharing pages including enforcing ownership rights independently of privilege level

Apparatus and method for handling write operations

Read ports and methods of outputting data via read ports

Write-through caching a JAVA® local variable within a register of a register bank

Communication of message signalled interrupts

Program instruction decompression and compression techniques

Enforcing data protection in an interconnect

Data access target predictions in a data processing system

PENTON ANTONY JOHN

Apparatus and method for error correction of data values in a storage device

Data processing apparatus and method for providing fault tolerance when executing a sequence of data processing operations

Handling of hard errors in a cache of a data processing apparatus

CRASKE SIMON JOHN

Error correction in a set associative storage device

Area and power efficient data coherency maintenance

SWAINE ANDREW BROOKFIELD

Generation of trace data in a multi-processor system

MACE TIMOTHY CHARLES

Communication using integrated circuit interconnect circuitry

VASEKIN VLADIMIR

Thread selection for multithreaded processing

GREENHALGH PETER RICHARD

Reducing errors in pre-decode caches

HORLEY JOHN MICHAEL

Generating a regularly synchronised count value

ROSE ANDREW CHRISTOPHER

System, method and computer program product for testing software