Inventor

RAMJI SHYAM

US45 patents

⚠️ This page may combine multiple inventors who share the name “RAMJI SHYAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAMJI SHYAM

IBM

Latch placement for high performance and low power circuits

Method for successive placement based refinement of a generalized cost function

Optimizing placement of circuit resources using a globally accessible placement memory

Optimizing placement of circuit resources using a globally accessible placement memory

Structured placement of latches/flip-flops to minimize clock power in high-performance designs

Clock power minimization with regular physical placement of clock repeater components

Legalization of VLSI circuit placement with blockages using hierarchical row slicing

Post-placement cell shifting

Method for legalizing the placement of cells in an integrated circuit layout

Optimizing placement of circuit resources using a globally accessible placement memory

Optimizing placement of circuit resources using a globally accessible placement memory

Large cluster persistence during placement optimization of integrated circuit designs

Detailed routability by cell placement

Memory element graph-based placement in integrated circuit design

Constraint-driven pin optimization for hierarchical design convergence

Structured placement of hierarchical soft blocks during physical synthesis of an integrated circuit

Propagating constants of structured soft blocks while preserving the relative placement structure

Hierarchically aware interior pinning for large synthesis blocks

Hierarchically aware interior pinning for large synthesis blocks

Rule check heatmap prediction

Streamlining data processing optimizations for machine learning workloads

Autonomous placement to satisfy self-aligned double patterning constraints

Enhancing stability of half perimeter wire length (HPWL)-driven analytical placement

Memory element graph-based placement in integrated circuit design

Thermally aware pin assignment and device placement

Merging of storage elements on multi-cycle signal distribution trees into multi-bit cells

Fraud detection using multi-task learning and/or deep learning

Model-based refinement of the placement process in integrated circuit generation

Large cluster persistence during placement optimization of integrated circuit designs

Optimizing placement of circuit resources using a globally accessible placement memory

Large cluster persistence during placement optimization of integrated circuit designs

Incremental timing optimization and placement

Hierarchical wire-pin co-optimization

Hierarchical wire-pin co-optimization

Scheduling for parallel processing of regionally-constrained placement problem

Hierarchy-driven logical and physical synthesis co-optimization

Critical path straightening system based on free-space aware and timing driven incremental placement

ALPERT CHARLES J

Local objective optimization in global placement of an integrated circuit design

Post-placement cell shifting

Separate refinement of local wirelength and local module density in intermediate placement of an integrated circuit design

Electronic design automation object placement with partially region-constrained objects

NAM GI-JOON

Scheduling for parallel processing of regionally-constrained placement problem

Scheduling for parallel processing of regionally-constrained placement problem

RAMJI SHYAM

Constraint programming based method for bus-aware macro-block pin placement in a hierarchical integrated circuit layout

KEINERT JOACHIM

Automatic positioning of gate array circuits in an integrated circuit design