Inventor
MORRISON MICHAEL J
US29 patents
⚠️ This page may combine multiple inventors who share the name “MORRISON MICHAEL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
11 patentsUS5961630AOct 5, 1999
Method and apparatus for handling dynamic structural hazards and exceptions by using post-ready latency
INTEL CORP70 citations96
US6412067B1Jun 25, 2002
Backing out of a processor architectural state
INTEL CORP21 citations92
US6279102B1Aug 21, 2001
Method and apparatus employing a single table for renaming more than one class of register
INTEL CORP36 citations92
US6223278B1Apr 24, 2001
Method and apparatus for floating point (FP) status word handling in an out-of-order (000) Processor Pipeline
INTEL CORP46 citations92
US6170052B1Jan 2, 2001
Method and apparatus for implementing predicated sequences in a processor with renaming
INTEL CORP36 citations92
US5996064ANov 30, 1999
Method and apparatus for guaranteeing minimum variable schedule distance by using post-ready latency
INTEL CORP44 citations92
US6094713AJul 25, 2000
Method and apparatus for detecting address range overlaps
INTEL CORP24 citations90
US5918031AJun 29, 1999
Computer utilizing special micro-operations for encoding of multiple variant code flows
INTEL CORP34 citations86
US5954814ASep 21, 1999
System for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a pipeline
INTEL CORP7 citations73
US5961615AOct 5, 1999
Method and apparatus for queuing data
INTEL CORP8 citations72
US6216221B1Apr 10, 2001
Method and apparatus for expanding instructions
INTEL CORP4 citations61
MOSYS INC
6 patentsUS10114558B2Oct 30, 2018
Integrated main memory and coprocessor with low latency
MOSYS INC7 citations84
US9354823B2May 31, 2016
Memory system including variable write burst and broadcast command scheduling
MOSYS INC3 citations73
US9529569B2Dec 27, 2016
Method and apparatus for randomizer
MOSYS INC2 citations62
US9971567B2May 15, 2018
Method and apparatus for randomizer
MOSYS INC0 citations52
US9921755B2Mar 20, 2018
Integrated main memory and coprocessor with low latency
MOSYS INC0 citations52
US8370725B2Feb 5, 2013
Communication interface and protocol
MOSYS INC1 citations48
MORRISON MICHAEL J
4 patentsUS8635417B2Jan 21, 2014
Memory system including variable write command scheduling
MORRISON MICHAEL J9 citations82
US8527676B2Sep 3, 2013
Reducing latency in serializer-deserializer links
MORRISON MICHAEL J6 citations82
US8832336B2Sep 9, 2014
Reducing latency in serializer-deserializer links
MORRISON MICHAEL J5 citations71
US8473695B2Jun 25, 2013
Memory system including variable write command scheduling
MORRISON MICHAEL J2 citations61
INTERSIL CORP
2 patentsINTERCONTINENTAL POTASH CORP USA
2 patentsUS8802048B2Aug 12, 2014
Methods of processing solutions of potassium sulfate and magnesium sulfate, methods of producing potassium sulfate, and related systems
INTERCONTINENTAL POTASH CORP USA7 citations79
US9139446B2Sep 22, 2015
Methods of processing solutions of potassium sulfate and magnesium sulfate, methods of producing potassium sulfate, and related systems
INTERCONTINENTAL POTASH CORP USA1 citations47