Inventor

JOYCE THOMAS F

US43 patents

⚠️ This page may combine multiple inventors who share the name “JOYCE THOMAS F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JOYCE THOMAS F

HONEYWELL INF SYSTEMS

Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization

Private cache-to-CPU interface in a bus oriented data processing system

Multi-configurable cache store system

First in first out activity queue for a cache store

High speed buffer memory system with word prefetch

Local bus interface for controlling information transfers between units in a central subsystem

Continuous updating of cache store

Microprogram memory bank addressing system

Out of store indicator for a cache store in test mode

Control store memory read error resiliency method and apparatus

Automatic rounding of floating point operands

Round robin replacement for a cache store

Microword address branching bit arrangement

Initialization of cache store to assure valid data

Distributed control store word architecture

Apparatus for performing the scientific add instruction

Stretch and stall clock

Word oriented high speed buffer memory system connected to a system bus

ROM-initializing apparatus

Automatic operand length control of the result of a scientific arithmetic operation

Microprogram splatter return apparatus

BULL HN INFORMATION SYST

Recovery method and apparatus for a pipelined processing unit of a multiprocessor system

Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution

Method and apparatus for avoiding processor deadly embrace in a multiprocessor system

Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units

Segment descriptor unit for performing static and dynamic address translation operations

Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols

Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus

Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy

External procedure invocation apparatus utilizing internal branch vector interrupts and vector address generation, in a RISC chip

Apparatus and method for address translation of non-aligned double word virtual addresses

Method for reexecuting instruction by altering high bits of instruction address based upon result of a subtraction operation with stored low bits

HONEYWELL BULL

Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page

High speed high density dynamic address translator

Least recently used replacement level generating apparatus

Multiprocessors on a single semiconductor chip

ZENITH DATA SYSTEMS CORP

Symmetric multiprocessing system with unified environment and distributed system functions

Symmetric multiprocessing system with unified environment and distributed system functions

PACKARD BELL NEC

Adaptively generating timing signals for access to various memory devices based on stored profiles

Symmetric multiprocessing system with unified environment and distributed system functions

NEC CORP

Symmetric multiprocessing system with unified environment and distributed system functions

Symmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address space

BULL NH INFORMATION SYSTEMS IN

Method and apparatus for backing out of a software instruction after execution has begun