Inventor
KELLY RICHARD P
US19 patents
⚠️ This page may combine multiple inventors who share the name “KELLY RICHARD P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HONEYWELL INF SYSTEMS
9 patentsUS4458308AJul 3, 1984
Microprocessor controlled communications controller having a stretched clock cycle
HONEYWELL INF SYSTEMS31 citations92
US4254462AMar 3, 1981
Hardware/firmware communication line adapter
HONEYWELL INF SYSTEMS35 citations92
US3938096AFeb 10, 1976
Apparatus for developing an address of a segment within main memory and an absolute address of an operand within the segment
HONEYWELL INF SYSTEMS70 citations92
US4641305AFeb 3, 1987
Control store memory read error resiliency method and apparatus
HONEYWELL INF SYSTEMS23 citations82
US4407014ASep 27, 1983
Communications subsystem having a direct connect clock
HONEYWELL INF SYSTEMS27 citations81
US4670835AJun 2, 1987
Distributed control store word architecture
HONEYWELL INF SYSTEMS11 citations74
US4494186AJan 15, 1985
Automatic data steering and data formatting mechanism
HONEYWELL INF SYSTEMS14 citations73
US4418384ANov 29, 1983
Communication subsystem with an automatic abort transmission upon transmit underrun
HONEYWELL INF SYSTEMS8 citations72
US4379340AApr 5, 1983
Communications subsystem idle link state detector
HONEYWELL INF SYSTEMS10 citations72
BULL HN INFORMATION SYST
8 patentsUS5193181AMar 9, 1993
Recovery method and apparatus for a pipelined processing unit of a multiprocessor system
BULL HN INFORMATION SYST102 citations96
US4980819ADec 25, 1990
Mechanism for automatically updating multiple unit register file memories in successive cycles for a pipelined processing system
BULL HN INFORMATION SYST30 citations92
US5123097AJun 16, 1992
Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy
BULL HN INFORMATION SYST18 citations74
US5179671AJan 12, 1993
Apparatus for generating first and second selection signals for aligning words of an operand and bytes within these words respectively
BULL HN INFORMATION SYST19 citations73
US5148530ASep 15, 1992
Method for reexecuting instruction by altering high bits of instruction address based upon result of a subtraction operation with stored low bits
BULL HN INFORMATION SYST6 citations63
US5197133AMar 23, 1993
Control store addressing from multiple sources
BULL HN INFORMATION SYST4 citations61
US5117491AMay 26, 1992
Ring reduction logic using parallel determination of ring numbers in a plurality of functional units and forced ring numbers by instruction decoding
BULL HN INFORMATION SYST2 citations61
US4916601AApr 10, 1990
Means for transferring firmware signals between a control store and a microprocessor means through a reduced number of connections by transfer according to firmware signal function
BULL HN INFORMATION SYST1 citations52