Inventor

CHENG YI-KAN

TW124 patents

⚠️ This page may combine multiple inventors who share the name “CHENG YI-KAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHENG YI-KAN

TAIWAN SEMICONDUCTOR MFG CO LTD

Integrated circuit with mixed row heights

Multi-patterning conflict free integrated circuit design

Method for generating layout diagram including cell having pin patterns and semiconductor device based on same

Multi-patterning system and method using pre-coloring or locked patterns

Method and system for replacing a pattern in a layout

Package structure and method for forming the same

Integrated circuit with mixed row heights

Method for manufacturing a cell having pins and semiconductor device based on same

Electromagnetic shielding metal-insulator-metal capacitor structure

Structure and method for cooling three-dimensional integrated circuits

Standard cells and variations thereof within a standard cell library

Electromagnetic shielding metal-insulator-metal capacitor structure

Techniques based on electromigration characteristics of cell interconnect

Structure and method for cooling three-dimensional integrated circuits

RC extraction for single patterning spacer technique

Interconnect structure and method for forming the same

Interconnect structure, semiconductor structure including interconnect structure and method for forming the same

Semiconductor device and method of manufacture

TAIWAN SEMICONDUCTOR MFG

Parasitic capacitance extraction for FinFETs

Table-based DFM for accurate post-layout analysis

Method and system for photomask assignment for double patterning technology

Multiple via connections using connectivity rings

Method and system for semiconductor simulation

Method, apparatus, and system for LPC hot spot fix

Method of designing fin field effect transistor (FinFET)-based circuit and system for implementing the same

Parasitic component library and method for efficient circuit design and simulation using the same

Method for shape and timing equivalent dimension extraction

Semiconductor device design method, system and computer-readable medium

Variation modeling

Double patterning technology (DPT) layout routing

Multi-patterning method

HSU CHIN-CHANG

Multi-patterning method

Methodology for analysis and fixing guidance of pre-coloring layout

Decomposition and marking of semiconductor device design layout in double patterning lithography

Multi-patterning method

SU KE-YING

Systems and methods for creating frequency-dependent netlist

Mask-shift-aware RC extraction for double patterning design

RC corner solutions for double patterning technology

CHENG YI-KAN

Routing method for double patterning design

Double patterning friendly lithography method and system

CHEN HUANG-YU

Routing system and method for double patterning technology

Method and system for replacing a pattern in a layout

LU LEE-CHUNG

Methods for cell boundary isolation in double patterning design

Mask-shift-aware RC extraction for double patterning design

HO CHIA-MING

Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process

LIN HUNG LUNG

Tool and method for eliminating multi-patterning conflicts

KUO CHIN-CHENG

Method of circuit design yield analysis

HUANG CHENG-I

RC extraction for single patterning spacer technique

HOU YUNG-CHIN

Integrated circuit design using DFM-enhanced architecture

LEE HUI YU

System and method for reducing layout-dependent effects