Inventor

CHEN HUANG-YU

TW56 patents

⚠️ This page may combine multiple inventors who share the name “CHEN HUANG-YU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN HUANG-YU

TAIWAN SEMICONDUCTOR MFG CO LTD

Cell layout of semiconductor device

Method of cutting conductive patterns

Method and system for replacing a pattern in a layout

Integrated circuit device and method

Circuit layouts and related methods

Cell layout of semiconductor device

Cell layout of semiconductor device

Method for checking and fixing double-patterning layout

Automated system and method for circuit design

Automated system and method for circuit design

Conductor scheme selection and track planning for mixed-diagonal-manhattan routing

Conductor scheme selection and track planning for mixed-diagonal-Manhattan routing

Integrated circuit device and method

Cell layout of semiconductor device

Method of cutting conductive patterns

Clock signal distribution system, integrated circuit device and method

Method of cutting conductive patterns

Automated system and method for circuit design

Method and associated system for circuit design

Diagonal torus network

Method of cutting conductive patterns

Duplicate layering and routing

Method for displaying timing information of an integrated circuit floorplan in real time

Stitch and trim methods for double patterning compliant standard cell design

Layout method and system for multi-patterning integrated circuits

Compression method and system for use with multi-patterning

Layout optimization for integrated circuit design

Layout optimization for integrated circuit design

TAIWAN SEMICONDUCTOR MFG

Layout re-decomposition for multiple patterning layouts

Multiple via connections using connectivity rings

Self-aligned multiple patterning layout design

Method for checking and fixing double-patterning layout

Double patterning technology (DPT) layout routing

Multiple via connections using connectivity rings

Method for displaying timing information of an integrated circuit floorplan

Reusable cut mask for multiple layers

Layout optimization for integrated design

Double patterning technology (DPT) layout routing

CHEN HUANG-YU

Compression method and system for use with multi-patterning

Cell layout for multiple patterning technology

Routing system and method for double patterning technology

Method and apparatus for achieving multiple patterning technology compliant design layout

Layout method and system for multi-patterning integrated circuits

Method and system for replacing a pattern in a layout

Chip-level ECO shrink

Double patterning technology using single-patterning-spacer-technique

LIN HUNG LUNG

Tool and method for eliminating multi-patterning conflicts

SU KE-YING

Systems and methods for creating frequency-dependent netlist

WANG CHUNG-HSING

Automatic place and route method for electromigration tolerant power distribution

HSIEH KEN-HSIEN

Double patterning methodology