Inventor

TAST HANS-WERNER

DE41 patents

⚠️ This page may combine multiple inventors who share the name “TAST HANS-WERNER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TAST HANS-WERNER

IBM

Token-based serialisation of instructions in a multiprocessor system

Apparatus and method for performing subroutine call and return operations

Method and system for a multi-level virtual/real cache system with synonym resolution

Register renaming with a pool of physical registers

Bus with request-dependent matching of the bandwidth available in both directions

Checkpointing a superscalar, out-of-order processor for error recovery

Hierarchical cache structure and handling thereof

Hierarchical cache structure and handling thereof

Hierarchical cache structure and handling thereof

Method, system, and computer program product for handling errors in a cache without processor core recovery

Electronic circuit for implementing a permutation operation

Data processing apparatus and method for correcting faulty microcode in a ROM device via a flag microinstruction in a RAM device including corrected microcode

Systems and methods for accessing cache memory

Hierarchical cache structure and handling thereof

Multiplexer

Evicting cached stores

Evicting cached stores

Method for executing branch instructions by processing loop end conditions in a second processor

Performance of a cache by detecting cache lines that have been reused

Method and system for fast access to a translation lookaside buffer

Store buffer for transactional memory

Generating a local clock domain using dynamic controls

Method and data processing system for data lookups

Store cache for transactional memory

Store cache for transactional memory

Managing transactional and non-transactional store observability

Controlling an unreliable data transfer in a data channel

Embedding of dynamic circuits in a static environment

Storage array allowing for multiple, simultaneous write accesses

Performance of a cache by detecting cache lines that have been reused

Systems and methods for adaptively mapping an instruction cache

HABERMANN CHRISTIAN

Method to verify an implemented coherency algorithm of a multi processor environment

Verification of logic circuit designs using dynamic clock gating

Data caching method

Data caching method

Avoiding cross-interrogates in a streaming data optimized L1 cache

Enhanced wiring structure for a cache supporting auxiliary data output

GLOBALFOUNDRIES INC

Handling virtual memory address synonyms in a multi-level cache hierarchy structure

ALEXANDER KHARY J

Managing transactional and non-transactional store observability

FEE MICHAEL

Handling corrupted background data in an out of order execution environment

PASCH EBERHARD

Cache bounded reference counting