Inventor

WANG CHUNG-HSING

TW204 patents

⚠️ This page may combine multiple inventors who share the name “WANG CHUNG-HSING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG CHUNG-HSING

TAIWAN SEMICONDUCTOR MFG CO LTD

Integrated circuit with mixed row heights

Power grid structures and method of forming the same

Systems and methods for context aware circuit design

Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

Integrated circuit design method, system and computer program product

Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same

Semiconductor device including PG-aligned cells and method of generating layout of same

Method for evaluating failure-in-time

Semiconductor device with reduced leakage current

Power grid of integrated circuit

Power gating for three dimensional integrated circuits (3DIC)

Method of generating techfile having reduced corner variation value

Method and system for replacing a pattern in a layout

Integrated circuit with thicker metal lines on lower metallization layer

Integrated circuit having a high cell density

Semiconductor arrangement and method of making

Integrated circuit device and method

System and computer program product for integrated circuit design

Integrated circuit with mixed row heights

Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

Circuit layouts and related methods

TAIWAN SEMICONDUCTOR MFG

Method of forming a layout including cells having different threshold voltages, a system of implementing and a layout formed

Methodology for generating a design rule check notch-error free core cell library layout

Semiconductor device design method, system and computer program product

Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization

Methodology of generating antenna effect models for library/IP in VLSI physical design

Power gating for three dimensional integrated circuits (3DIC)

Cell and macro placement on fin grid

Channel doping extension beyond cell boundaries

Layout re-decomposition for multiple patterning layouts

Integrated circuit with standard cells

Multiple via connections using connectivity rings

Place-and-route layout method with same footprint cells

Design flow for shrinking circuits having non-shrinkable IP layout

System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE)

Pattern matching based parasitic extraction with pattern reuse

Verification of 3D integrated circuits

System and method for testing state retention circuits

WANG CHUNG-HSING

Verification of 3D integrated circuits

Automatic place and route method for electromigration tolerant power distribution

System and method for observing threshold voltage variations

CHEN HUANG-YU

Compression method and system for use with multi-patterning

Method and system for replacing a pattern in a layout

DYNACOLOR INC

Camera

Camera

SU KE-YING

Systems and methods for creating frequency-dependent netlist

Mask-shift-aware RC extraction for double patterning design

LIN HUNG LUNG

Tool and method for eliminating multi-patterning conflicts

LIU HUNG-YI

Method for dummy metal and dummy via insertion

LU LEE-CHUNG

System and method for on-chip-variation analysis