Inventor

NASSIF SANI R

US63 patents

⚠️ This page may combine multiple inventors who share the name “NASSIF SANI R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NASSIF SANI R

IBM

Method and computer program for efficient cell failure rate estimation in cell arrays

Method for determining the leakage power for an integrated circuit

Split-layer design for double patterning lithography

Energy efficient storage device using per-element selectable power supply voltages

Scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics

Characterization array and method for determining threshold voltage variation

Radiation therapy treatment planning using regression

Method for determining and using leakage current sensitivities to optimize the design of an integrated circuit

Statistical design with importance sampling reuse

Broken-spheres methodology for improved failure probability analysis in multi-fail regions

Equivalent device statistical modeling for bitline leakage modeling

Method and computer program for controlling a storage device having per-element selectable power supply voltages

Delay-based bias temperature instability recovery measurements for characterizing stress degradation and recovery

Method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects

Characterization circuit for fast determination of device capacitance variation

Method and system for determining element voltage selection control values for a storage device

Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks

Method and apparatus for measuring device mismatches

Fast and accurate proton therapy dose calculations

Translating different clinical protocols for particle therapy into a set of constraints

Power and performance sorting of microprocessors from first interconnect layer to wafer final test

Statistical design with importance sampling reuse

Test system and computer program for determining threshold voltage variation using a device array

Scannable virtual rail ring oscillator circuit and system for measuring variations in device characteristics

Method for determining threshold voltage variation using a device array

Characterization array circuit

Method of separating the process variation in threshold voltage and effective channel length by electrical measurements

Calibration of non-contact current sensors

Closed-loop modeling of gate leakage for fast simulators

Method and apparatus for measuring device mismatches

Statistical design with importance sampling reuse

Circuit for computing moment pre-products for statistical analysis

Extracting protobeams for cancer radiation therapy

JOSHI RAJIV V

Methodology for correlated memory fail estimations

On-chip leakage current modeling and measurement circuit

Methodology for correlated memory fail estimations

Computer program product for controlling a storage device having per-element selectable power supply voltages

On-chip leakage current modeling and measurement circuit

Equivalent device statistical modeling for bitline leakage modeling

AGARWAL KANAK B

Model-based retargeting of layout patterns for sub-wavelength photolithography

Optical proximity correction for improved electrical characteristics

Method and test system for fast determination of parameter variation statistics

GEBARA FADI H

Test circuit for bias temperature instability recovery measurements

Test circuit for bias temperature instability recovery measurements

ABOU GHAIDA RANI S

Multiple patterning layout decomposition for ease of conflict removal

Mask assignment for multiple patterning lithography

EL-ESSAWY WAEL

Calibration of non-contact current sensors

Calibration of non-contact voltage sensors

LIU YING

Gradient based search mechanism for optimizing photolithograph masks

ACAR EMRAH

Compensating for variations in device characteristics in integrated circuit simulation