Inventor

IGURA HIROYUKI

JP24 patents

⚠️ This page may combine multiple inventors who share the name “IGURA HIROYUKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IGURA HIROYUKI

NEC CORP

Multiprocessor system having shared buses, prioritized arbitration, and clock synchronization circuitry

Phase locked loop circuit with high stability having a reset signal generating circuit

Clock input control circuit

Exclusive-OR gate, an inverted type selector, and adders

Position estimation apparatus, position estimation system, position estimation method and recording medium for position estimation

Wireless communication apparatus, data reception method, and program

Patch array antenna, directivity control method therefor and wireless device using patch array antenna

Circuit for recording digital waveform data and method of doing the same

Processor

Signal generator, signal generation method, and numerically controlled oscillator

Radio reception circuit, radio reception method, and radio reception program

Multi-stage filter processing device and method

IGURA HIROYUKI

Deadlock avoidance method and deadlock avoidance mechanism

FFT computing apparatus and power computing method

Digital signal processor, program control method, and control program

Information processing device and task switching method

Channel estimate interpolation circuit and method

Likelihood value calculation device, likelihood value calculation method, and radio system

TAKEUCHI TOSHIKI

Encoding/decoding processor and wireless communication apparatus

Multi-processor system and controlling method thereof

Data encryption/decryption method and data processing device

Co-processor for complex arithmetic processing, and processor system

Multiprocessor system, execution control method and execution control program

CHONG SHENG WEI

Interleaver with parallel address queue arbitration dependent on which queues are empty