Inventor

CHANDRA ANSHUMAN

US7 patents

⚠️ This page may combine multiple inventors who share the name “CHANDRA ANSHUMAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SYNOPSYS INC

4 patents

US10621298B2Apr 14, 2020

Automatically generated schematics and visualization

SYNOPSYS INC0 citations48

US10067187B2Sep 4, 2018

Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment

SYNOPSYS INC0 citations48

US9417287B2Aug 16, 2016

Scheme for masking output of scan chains in test circuit

SYNOPSYS INC0 citations47

US9239897B2Jan 19, 2016

Hierarchical testing architecture using core circuit with pseudo-interfaces

SYNOPSYS INC1 citations47

KAPUR ROHIT

1 patent

US8065651B2Nov 22, 2011

Implementing hierarchical design-for-test logic for modular circuit design

KAPUR ROHIT24 citations88

CHANDRA ANSHUMAN

1 patent

US8479067B2Jul 2, 2013

Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry

CHANDRA ANSHUMAN12 citations77

TAIWAN SEMICONDUCTOR MFG CO LTD

1 patent

US12066490B2Aug 20, 2024

Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis

TAIWAN SEMICONDUCTOR MFG CO LTD1 citations61