Inventor

SAIKIA JYOTIRMOY

IN9 patents

⚠️ This page may combine multiple inventors who share the name “SAIKIA JYOTIRMOY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SYNOPSYS INC

5 patents

US8954918B2Feb 10, 2015

Test design optimizer for configurable scan architectures

SYNOPSYS INC2 citations57

US10203370B2Feb 12, 2019

Scheme for masking output of scan chains in test circuit

SYNOPSYS INC0 citations51

US9588179B2Mar 7, 2017

Scheme for masking output of scan chains in test circuit

SYNOPSYS INC0 citations51

US10067187B2Sep 4, 2018

Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment

SYNOPSYS INC0 citations48

US9417287B2Aug 16, 2016

Scheme for masking output of scan chains in test circuit

SYNOPSYS INC0 citations47

KAPUR ROHIT

2 patents

US8065651B2Nov 22, 2011

Implementing hierarchical design-for-test logic for modular circuit design

KAPUR ROHIT24 citations88

US8584073B2Nov 12, 2013

Test design optimizer for configurable scan architectures

KAPUR ROHIT7 citations77

CHANDRA ANSHUMAN

1 patent

US8479067B2Jul 2, 2013

Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry

CHANDRA ANSHUMAN12 citations77

KUMAR ASHWIN

1 patent

US8521464B2Aug 27, 2013

Accelerating automatic test pattern generation in a multi-core computing environment via speculatively scheduled sequential multi-level parameter value optimization

KUMAR ASHWIN1 citations46