Inventor
CHAN CHUNG-LUN
US7 patents
⚠️ This page may combine multiple inventors who share the name “CHAN CHUNG-LUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
6 patentsUS10108554B2Oct 23, 2018
Apparatuses, methods, and systems to share translation lookaside buffer entries
INTEL CORP7 citations80
US9875185B2Jan 23, 2018
Memory sequencing with coherent and non-coherent sub-systems
INTEL CORP2 citations72
US10261904B2Apr 16, 2019
Memory sequencing with coherent and non-coherent sub-systems
INTEL CORP0 citations51
US9715432B2Jul 25, 2017
Memory fault suppression via re-execution and hardware FSM
INTEL CORP1 citations50
US10318427B2Jun 11, 2019
Resolving memory accesses crossing cache line boundaries
INTEL CORP0 citations38
US9886396B2Feb 6, 2018
Scalable event handling in multi-threaded processor cores
INTEL CORP0 citations35