Inventor
ROTEM SHAI
IL25 patents
⚠️ This page may combine multiple inventors who share the name “ROTEM SHAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
22 patentsUS5265227ANov 23, 1993
Parallel protection checking in an address translation look-aside buffer
INTEL CORP59 citations96
US7664970B2Feb 16, 2010
Method and apparatus for a zero voltage processor sleep state
INTEL CORP38 citations94
US7523327B2Apr 21, 2009
System and method of coherent data transfer during processor idle states
INTEL CORP19 citations92
US6314553B1Nov 6, 2001
Circuit synthesis and verification using relative timing
INTEL CORP29 citations92
US5948096ASep 7, 1999
Apparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytes
INTEL CORP36 citations91
US5931944AAug 3, 1999
Branch instruction handling in a self-timed marking system
INTEL CORP49 citations91
US5465216ANov 7, 1995
Automatic design verification
INTEL CORP80 citations91
US5574872ANov 12, 1996
Method and apparatus for controlling the saving of pipelines in pipelined processors during trap handling
INTEL CORP26 citations89
US7112979B2Sep 26, 2006
Testing arrangement to distribute integrated circuits
INTEL CORP12 citations83
US5978899ANov 2, 1999
Apparatus and method for parallel processing and self-timed serial marking of variable length instructions
INTEL CORP18 citations82
US5941982AAug 24, 1999
Efficient self-timed marking of lengthy variable length instructions
INTEL CORP13 citations72
US9841807B2Dec 12, 2017
Method and apparatus for a zero voltage processor sleep state
INTEL CORP1 citations62
US9141180B2Sep 22, 2015
Method and apparatus for a zero voltage processor sleep state
INTEL CORP1 citations62
US10955885B2Mar 23, 2021
Methods and systems to control power gates during an active state of a gated domain based on load conditions of the gated domain
INTEL CORP1 citations61
US7233162B2Jun 19, 2007
Arrangements having IC voltage and thermal resistance designated on a per IC basis
INTEL CORP3 citations61
US7109737B2Sep 19, 2006
Arrangements having IC voltage and thermal resistance designated on a per IC basis
INTEL CORP4 citations61
US9874925B2Jan 23, 2018
Method and apparatus for a zero voltage processor sleep state
INTEL CORP0 citations52
US9870044B2Jan 16, 2018
Method and apparatus for a zero voltage processor sleep state
INTEL CORP0 citations52
US9235258B2Jan 12, 2016
Method and apparatus for a zero voltage processor
INTEL CORP0 citations52
US9223389B2Dec 29, 2015
Method and apparatus for a zero voltage processor
INTEL CORP0 citations52
US9223390B2Dec 29, 2015
Method and apparatus for a zero voltage processor
INTEL CORP0 citations52
US10536139B2Jan 14, 2020
Charge-saving power-gate apparatus and method
INTEL CORP0 citations50