Inventor
LEE JOE
US45 patents
⚠️ This page may combine multiple inventors who share the name “LEE JOE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
29 patentsUS9349687B1May 24, 2016
Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect
IBM96 citations98
US10020255B1Jul 10, 2018
Integration of super via structure in BEOL
IBM36 citations94
US10020254B1Jul 10, 2018
Integration of super via structure in BEOL
IBM39 citations94
US9953865B1Apr 24, 2018
Structure and method to improve FAV RIE process margin and electromigration
IBM23 citations94
US9373582B1Jun 21, 2016
Self aligned via in integrated circuit
IBM18 citations92
US10622301B2Apr 14, 2020
Method of forming a straight via profile with precise critical dimension control
IBM8 citations84
US9390967B2Jul 12, 2016
Method for residue-free block pattern transfer onto metal interconnects for air gap formation
IBM9 citations84
US9385078B1Jul 5, 2016
Self aligned via in integrated circuit
IBM11 citations83
US11037822B2Jun 15, 2021
Svia using a single damascene interconnect
IBM2 citations73
US10672705B2Jun 2, 2020
Method of forming a straight via profile with precise critical dimension control
IBM3 citations73
US10347825B2Jul 9, 2019
Selective deposition and nitridization of bottom electrode metal for MRAM applications
IBM3 citations73
US10312434B2Jun 4, 2019
Selective deposition and nitridization of bottom electrode metal for MRAM applications
IBM4 citations73
US10276436B2Apr 30, 2019
Selective recessing to form a fully aligned via
IBM2 citations73
US10121676B2Nov 6, 2018
Interconnects fabricated by hydrofluorocarbon gas-assisted plasma etch
IBM2 citations73
US10049974B2Aug 14, 2018
Metal silicate spacers for fully aligned vias
IBM4 citations73
US9905513B1Feb 27, 2018
Selective blocking boundary placement for circuit locations requiring electromigration short-length
IBM2 citations73
US9252051B1Feb 2, 2016
Method for top oxide rounding with protection of patterned features
IBM3 citations73
US12400859B2Aug 26, 2025
Metal hard mask for precise tuning of mandrels
IBM0 citations63
US12266607B2Apr 1, 2025
Bottom barrier free interconnects without voids
IBM0 citations62
US11366671B2Jun 21, 2022
Completion mechanism for a microprocessor instruction completion table
IBM0 citations62
US11164815B2Nov 2, 2021
Bottom barrier free interconnects without voids
IBM0 citations62
US9768113B2Sep 19, 2017
Self aligned via in integrated circuit
IBM1 citations62
US10643859B2May 5, 2020
Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication
IBM0 citations52
US10211138B2Feb 19, 2019
Metal silicate spacers for fully aligned vias
IBM0 citations52
US10170416B2Jan 1, 2019
Selective blocking boundary placement for circuit locations requiring electromigration short-length
IBM0 citations52
US9934984B2Apr 3, 2018
Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication
IBM0 citations52
US10831489B2Nov 10, 2020
Mechanism for completing atomic instructions in a microprocessor
IBM0 citations51
US10725786B2Jul 28, 2020
Completion mechanism for a microprocessor instruction completion table
IBM0 citations51
US10713057B2Jul 14, 2020
Mechanism to stop completions using stop codes in an instruction completion table
IBM0 citations51
TESSERA INC
5 patentsUS10985056B2Apr 20, 2021
Structure and method to improve FAV RIE process margin and Electromigration
TESSERA INC2 citations73
US10957584B2Mar 23, 2021
Structure and method to improve FAV RIE process margin and electromigration
TESSERA INC1 citations73
US11257717B2Feb 22, 2022
Selective recessing to form a fully aligned via
TESSERA INC0 citations62
US10832952B2Nov 10, 2020
Selective recessing to form a fully aligned via
TESSERA INC0 citations52
US10636706B2Apr 28, 2020
Selective recessing to form a fully aligned via
TESSERA INC0 citations52