Inventor
AUDET JEAN
CA36 patents
⚠️ This page may combine multiple inventors who share the name “AUDET JEAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
35 patentsUS7268570B1Sep 11, 2007
Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip
IBM24 citations91
US10784202B2Sep 22, 2020
High-density chip-to-chip interconnection with silicon bridge
IBM33 citations89
US9673064B2Jun 6, 2017
Interposer with lattice construction and embedded conductive metal structures
IBM4 citations84
US9443799B2Sep 13, 2016
Interposer with lattice construction and embedded conductive metal structures
IBM9 citations84
US6762367B2Jul 13, 2004
Electronic package having high density signal wires with low resistance
IBM13 citations84
US7420378B2Sep 2, 2008
Power grid structure to optimize performance of a multiple core processor
IBM12 citations83
US11209598B2Dec 28, 2021
Photonics package with face-to-face bonding
IBM11 citations82
US9553079B1Jan 24, 2017
Flip chip assembly with connected component
IBM7 citations80
US7454833B2Nov 25, 2008
High performance chip carrier substrate
IBM6 citations74
US7214886B2May 8, 2007
High performance chip carrier substrate
IBM7 citations74
US10622299B2Apr 14, 2020
Multi terminal capacitor within input output path of semiconductor package interconnect
IBM1 citations73
US10460956B2Oct 29, 2019
Interposer with lattice construction and embedded conductive metal structures
IBM1 citations73
US7017128B2Mar 21, 2006
Concurrent electrical signal wiring optimization for an electronic package
IBM8 citations73
US6703706B2Mar 9, 2004
Concurrent electrical signal wiring optimization for an electronic package
IBM8 citations73
US10211174B2Feb 19, 2019
Flip chip assembly with connected component
IBM3 citations69
US7066740B2Jun 27, 2006
Area array package with low inductance connecting device
IBM7 citations69
US7868459B2Jan 11, 2011
Semiconductor package having non-aligned active vias
IBM2 citations63
US7863526B2Jan 4, 2011
High performance chip carrier substrate
IBM2 citations63
US11388821B2Jul 12, 2022
Thin film capacitors for core and adjacent build up layers
IBM0 citations62
US7667470B2Feb 23, 2010
Power grid structure to optimize performance of a multiple core processor
IBM3 citations62
US10949600B2Mar 16, 2021
Semiconductor package floating metal checks
IBM0 citations60
US7482180B1Jan 27, 2009
Method for determining the impact of layer thicknesses on laminate warpage
IBM3 citations60
US10813215B2Oct 20, 2020
Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance
IBM0 citations52
US10806030B2Oct 13, 2020
Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance
IBM0 citations52
US10687420B2Jun 16, 2020
Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance
IBM0 citations52
US10224274B2Mar 5, 2019
Multi terminal capacitor within input output path of semiconductor package interconnect
IBM0 citations52
US10224273B2Mar 5, 2019
Multi terminal capacitor within input output path of semiconductor package interconnect
IBM0 citations52
US9899313B2Feb 20, 2018
Multi terminal capacitor within input output path of semiconductor package interconnect
IBM0 citations52
US7886435B2Feb 15, 2011
High performance chip carrier substrate
IBM0 citations52
US7786579B2Aug 31, 2010
Apparatus for crack prevention in integrated circuit packages
IBM1 citations52
US10660209B2May 19, 2020
Thin film capacitors for core and adjacent build up layers
IBM0 citations51
US10423751B2Sep 24, 2019
Semiconductor package floating metal checks
IBM0 citations50
US6461443B1Oct 8, 2002
Method and apparatus for continuous cleaning of substrate surfaces using ozone
IBM3 citations49
US9984988B2May 29, 2018
Flip chip assembly with connected component
IBM0 citations48
US10706204B2Jul 7, 2020
Automated generation of surface-mount package design
IBM0 citations38