Inventor
WITTERS LIESBETH
BE21 patents
⚠️ This page may combine multiple inventors who share the name “WITTERS LIESBETH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IMEC VZW
16 patentsUS10269929B2Apr 23, 2019
Internal spacer formation for nanowire semiconductor devices
IMEC VZW10 citations82
US9842777B2Dec 12, 2017
Semiconductor devices comprising multiple channels and method of making same
IMEC VZW12 citations82
US9633891B2Apr 25, 2017
Method for forming a transistor structure comprising a fin-shaped channel structure
IMEC VZW4 citations72
US10361268B2Jul 23, 2019
Internal spacers for nanowire semiconductor devices
IMEC VZW3 citations70
US10090393B2Oct 2, 2018
Method for forming a field effect transistor device having an electrical contact
IMEC VZW2 citations70
US11195767B2Dec 7, 2021
Integration of a III-V device on a Si substrate
IMEC VZW1 citations61
US9478544B2Oct 25, 2016
Method for forming a germanium channel layer for an NMOS transistor device, NMOS transistor device and CMOS device
IMEC VZW2 citations60
US11355618B2Jun 7, 2022
Low parasitic Ccb heterojunction bipolar transistor
IMEC VZW0 citations53
US9299563B2Mar 29, 2016
Method for forming a strained semiconductor structure
IMEC VZW0 citations51
US11557503B2Jan 17, 2023
Method for co-integration of III-V devices with group IV devices
IMEC VZW0 citations50
US11387350B2Jul 12, 2022
Semiconductor fin structure and method of fabricating the same
IMEC VZW0 citations50
US10714595B2Jul 14, 2020
Method of forming a semiconductor device comprising at least one germanium nanowire
IMEC VZW0 citations50
US9502415B2Nov 22, 2016
Method for providing an NMOS device and a PMOS device on a silicon substrate and silicon substrate comprising an NMOS device and a PMOS device
IMEC VZW1 citations50
US11646200B2May 9, 2023
Integration of a III-V construction on a group IV substrate
IMEC VZW0 citations48
US9343329B2May 17, 2016
Contact formation in Ge-containing semiconductor devices
IMEC VZW0 citations43
US9972622B2May 15, 2018
Method for manufacturing a CMOS device and associated device
IMEC VZW0 citations40
IMEC
5 patentsUS9476143B2Oct 25, 2016
Methods using mask structures for substantially defect-free epitaxial growth
IMEC7 citations84
US9070712B2Jun 30, 2015
Methods for manufacturing a field-effect semiconductor device
IMEC7 citations83
US9123566B2Sep 1, 2015
Complementary metal-oxide-semiconductor device comprising silicon and germanium and method for manufacturing thereof
IMEC16 citations81
US10340139B2Jul 2, 2019
Methods and mask structures for substantially defect-free epitaxial growth
IMEC0 citations52
US8828826B2Sep 9, 2014
Method for manufacturing a transistor device comprising a germanium based channel layer
IMEC1 citations50